Abstract: Methods for improving an implementation of a design in a programmable logic device (PLD). A topological level of the design implementation is determined for each look-up table (LUT) of the PLD. A subset of the LUTs that are on the critical timing paths of the design implementation is determined. For each LUT in the subset at each topological level, a set combinations is determined for assigning signals to the inputs of the LUT. A current assignment of the signals to the LUT inputs is initialized according to the design implementation. For each LUT in the subset at each topological level, the method determines whether a respective assignment for each combination in the set for the LUT improves a timing metric for the LUT relative to the current assignment for the LUT, and the current assignment is updated when the respective assignment improves the timing metric for the LUT.

Abstract: Methods of routing user designs in programmable logic devices (PLDs) having heterogeneous routing structures, i.e., PLDs including both high-power and low-power interconnect resources. A first pass routing step is performance-based, e.g., utilizes a cost function biased towards the high-power interconnect resources. The first routed design is then evaluated to identify non-critical nets in the first routed design that can yield the most power-saving benefit by being retargeted to the low-power interconnect resources. For example, a sorted list of nets can be created in which the identified nets are evaluated based on the capacitance per load pin of each net. A second pass routing step is then performed, e.g., rerouting the nets identified as being non-critical and having the greatest potential power-saving benefit. In some embodiments, the permitted increase in the delay of each rerouted net is bound by the slack of the net as routed in the first routed design.

Abstract: A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.

Abstract: Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.

Abstract: Within a computer automated tool, a method of physical circuit design can include assigning initial locations to components in the circuit design and determining an initial routing of connections between components in the circuit design using an overlap mode. The method also can include determining timing critical connections and selectively relocating components with at least one timing critical connection prior to performing a detailed routing of the circuit design.

Abstract: Within a computer automated tool, a method (400) of estimating an upper-bound of an operational frequency of at least a portion of a placed circuit design can include identifying (405) a clock source within the placed circuit design, wherein the clock source is associated with a clock domain, and determining (410) an initial routing of the clock domain. The method also can include determining (420) a minimum path slack corresponding to each connection of the clock domain. Connections of the clock domain which have a lowest minimum path slack can be marked (430). One or more marked connections which are not routed in delay mode can be identified and routed in delay mode (455) allowing sharing of routing resources by different nets.

Abstract: A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock signals to the clock pin nodes are determined. The routing tree is balanced to a target clock skew, such as zero clock skew, for the clock signals provided to the clock pin nodes. Programmable interconnect circuits are selectively added to reduce clock skews of the clock signals, where the clock skews being reduced at the clock pin nodes are for at least a portion of the clock pin nodes. Additionally described are determining clock propagation delays to clock pins and balancing a clock tree using computer aided design.

Abstract: Method and apparatus is described for interconnect routing. More particularly, an integrated circuit may be thought of as a network with a plurality of resources that are interconnected. These resources may be blocks of circuitry or individual circuit elements. By first routing in a resource mode, critical connections are identifiable. After that routing, a deterministic approach to delay mode routing is described using logic level information. Connections within a logic level are independent, thereby allowing multiple connections for a logic level to be routed together without any need for timing update.