Patents by Inventor Anirban Ray

Anirban Ray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200272530
    Abstract: A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Samir Mittal, Gurpreet Anand, Anirban Ray, Parag R. Maharana
  • Patent number: 10691611
    Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: store a memory ratio in association with a context of executing instructions; execute a set of instructions in the context; allocate, for execution of the set of instructions in the context, an amount of memory, including an amount of the first memory and an amount of the second memory; and access the amount of the second memory via the amount of the first memory during the execution of the set of instructions in the context. A ratio between the amount of the first memory and an amount of the second memory allocated for the execution of the set of instructions in the context is in accordance with the memory ratio.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Anirban Ray, Parag R. Maharana
  • Patent number: 10671460
    Abstract: A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Samir Mittal, Gurpreet Anand, Anirban Ray, Parag R. Maharana
  • Publication number: 20200089610
    Abstract: A system includes a first memory component of a first memory type, a second memory component of a second memory type with a higher access latency than the first memory component, and a third memory component of a third memory type with a higher access latency than the first and second memory components. The system further includes a processing device to identify a section of a data page stored in the first memory component, and access patterns associated with the data page and the section of the data page. The processing device determines to cache the data page at the second memory component based on the access patterns, copying the section of the data page stored in the first memory component to the second memory component. The processing device then copies additional sections of the data page stored at the third memory component to the second memory component.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 19, 2020
    Inventors: Paul STONELAKE, Horia C. SIMIONESCU, Samir MITTAL, Robert M. WALKER, Anirban RAY, Gurpreet ANAND
  • Publication number: 20200042246
    Abstract: A system controller, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, wherein each of the plurality of virtual memory controllers is associated with a different portion of the one or more memory devices, and provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The system controller further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, the host computing system to assign each of the plurality of physical functions to a different virtual machine running on the host computing system.
    Type: Application
    Filed: March 15, 2019
    Publication date: February 6, 2020
    Inventors: Parag R. Maharana, Anirban Ray, Gurpreet Anand, Samir Rajadnya, Paul Stonelake, Samir Mittal
  • Publication number: 20200019506
    Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 16, 2020
    Inventors: Anirban Ray, Samir Mittal, Gurpreet Anand, Parag R. Maharana
  • Publication number: 20200019510
    Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: store a memory ratio in association with a context of executing instructions; execute a set of instructions in the context; allocate, for execution of the set of instructions in the context, an amount of memory, including an amount of the first memory and an amount of the second memory; and access the amount of the second memory via the amount of the first memory during the execution of the set of instructions in the context. A ratio between the amount of the first memory and an amount of the second memory allocated for the execution of the set of instructions in the context is in accordance with the memory ratio.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 16, 2020
    Inventors: Anirban Ray, Parag R. Maharana
  • Publication number: 20190253520
    Abstract: A memory system having one or more memory components and a controller. The controller can receive access requests from a communication connection. The access requests can identify data items associated with the access requests, addresses of the data items, and contexts of the data items in which the data items are used for the access requests. The controller can identify separate memory regions for separate contexts respectively, determine placements of the data items in the separate memory regions based on the contexts of the data items, and determine a mapping between the addresses of the data items and memory locations that are within the separate memory regions corresponding to the contexts of the data items. The memory system stores store the data items at the memory locations separated by different memory regions according to different contexts.
    Type: Application
    Filed: November 7, 2018
    Publication date: August 15, 2019
    Inventors: Parag R. Maharana, Anirban Ray, Gurpreet Anand
  • Publication number: 20190243756
    Abstract: A computing system having at least one bus, a plurality of different memory components, and a processing device operatively coupled with the plurality of memory components through the at least one bus. The different memory components include first memory and second memory having different memory access speeds. The computing system further includes a memory virtualizer operatively to: store an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory; monitor usages of the first memory and the second memory; adjust the address map based on the usages to improve speed of the processing device in memory access involving the first memory and the second memory; and swap data content in the first memory and the second memory according to adjustments to the address map.
    Type: Application
    Filed: August 3, 2018
    Publication date: August 8, 2019
    Inventors: Anirban Ray, Parag R. Maharana, Gurpreet Anand
  • Publication number: 20190243570
    Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.
    Type: Application
    Filed: August 3, 2018
    Publication date: August 8, 2019
    Inventors: Samir Mittal, Anirban Ray, Gurpreet Anand
  • Publication number: 20190243695
    Abstract: A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.
    Type: Application
    Filed: August 3, 2018
    Publication date: August 8, 2019
    Inventors: Samir Mittal, Gurpreet Anand, Anirban Ray, Parag R. Maharana
  • Publication number: 20190243552
    Abstract: A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.
    Type: Application
    Filed: August 21, 2018
    Publication date: August 8, 2019
    Inventors: Parag R. Maharana, Anirban Ray, Gurpreet Anand, Samir Mittal
  • Patent number: 9790175
    Abstract: In the present disclosure there is provided a process for obtaining di-sulfide oil having sodium level below 0.1 ppm wherein a stream comprising di-sulfide oil having sodium level 1 ppm, collected as a waste stream from LPG desulfurization unit, is passed through an alumina bed packed in a column at a pre-determined liquid hourly space velocity (LHSV) and at pre-determined temperature to obtain a treated stream comprising di-sulfide oil having sodium level below 0.1 ppm.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: October 17, 2017
    Assignee: Reliance Industries Limited
    Inventors: Biswajit Shown, Nagarathinam Shenbaga Murthy, Asit Kumar Das, Swapan Ghosh, Bidhayak Das, Rajeshwer Dongara, Anirban Ray, Chirag Dalpatbhai Panseriya, Udayan Sivathanu Ramalakshmi, Atul Kathiria
  • Publication number: 20160362363
    Abstract: In the present disclosure there is provided a process for obtaining di-sulfide oil having sodium level below 0.1 ppm wherein a stream comprising di-sulfide oil having sodium level 1 ppm, collected as a waste stream from LPG desulfurization unit, is passed through an alumina bed packed in a column at a pre-determined liquid hourly space velocity (LHSV) and at pre-determined temperature to obtain a treated stream comprising di-sulfide oil having sodium level below 0.1 ppm.
    Type: Application
    Filed: March 13, 2015
    Publication date: December 15, 2016
    Applicant: Reliance Industries Limited
    Inventors: Biswajit Shown, Nagarathinam Shenbaga Murthy, Asit Kumar Das, Swapan Ghosh, Bidhayak Das, Rajeshwer Dongara, Anirban Ray, Chirag Dalpatbhai Panseriya, Udayan Sivathanu Ramalakshmi, Atul Kathiria
  • Publication number: 20130198113
    Abstract: A method that knits together and logically sequences diverse services such as, but not limited to, social networks, financial services, news feeds, email services, calendar services, analytical platforms and Business-to-consumer (B2C) services to create a state full cohesive end-to-end user experience on a single intelligent collaboration platform spanning across web, mobile and cloud.
    Type: Application
    Filed: January 28, 2012
    Publication date: August 1, 2013
    Inventors: Anirban Ray, Satadal Bhattalharjee