Abstract: The present disclosure provides a duty locked loop circuit that includes a switch network including a first electronic switch device controlled by a first control signal that is based on a first input signal and a second electronic switch device controlled by a second control signal that is based on a second input signal. The duty locked loop circuit includes an integrator circuit electrically connected to the switch network. The integrator circuit is configured to generate an output voltage proportional to an integral of a difference between a first duty cycle of the first input signal and a second duty cycle of the second input signal. The duty locked loop circuit includes an output circuit configured to generate an output signal having an output duty cycle that is based on the output voltage.

Abstract: The present disclosure provides a duty locked loop circuit that includes a switch network including a first electronic switch device controlled by a first control signal that is based on a first input signal and a second electronic switch device controlled by a second control signal that is based on a second input signal. The duty locked loop circuit includes an integrator circuit electrically connected to the switch network. The integrator circuit is configured to generate an output voltage proportional to an integral of a difference between a first duty cycle of the first input signal and a second duty cycle of the second input signal. The duty locked loop circuit includes an output circuit configured to generate an output signal having an output duty cycle that is based on the output voltage.

Abstract: Certain aspects of the present disclosure provide an apparatus for noise cancellation. One example apparatus generally includes a first delay path and a second delay path, each providing signals generated by applying a different delay to an input signal, and a first comparator having a first input coupled to the first delay path and a second input coupled to the second delay path. The apparatus also includes a switching circuit having a control input coupled to an output of the first comparator, the switching circuit configured to selectively couple the first delay path or the second delay path to an output node of the switching circuit based on a signal at the control input. The apparatus also includes an attenuation circuit having a first input coupled to an input path for providing the input signal, and a second input coupled to the output node of the switching circuit.

Abstract: In one embodiment, a circuit includes a first amplifier having a first differential input, a second differential input, and an output. The replica device is configured to generate a replica current of a current flowing through the battery where the first amplifier controls the control device to control the replica current. The circuit also includes a second amplifier having a third differential input, a fourth differential input, and an output. The second amplifier is configured to compensate for a first offset error of the first amplifier and a second offset error of the second amplifier based on selectively coupling the third differential input to the output of the first amplifier during a first phase, selectively coupling the output of the second amplifier to the second differential input during the first phase, and selectively coupling the output of the second amplifier to the fourth differential input during a second phase.

Abstract: In one embodiment, a circuit includes a first amplifier having a first differential input, a second differential input, and an output. The replica device is configured to generate a replica current of a current flowing through the battery where the first amplifier controls the control device to control the replica current. The circuit also includes a second amplifier having a third differential input, a fourth differential input, and an output. The second amplifier is configured to compensate for a first offset error of the first amplifier and a second offset error of the second amplifier based on selectively coupling the third differential input to the output of the first amplifier during a first phase, selectively coupling the output of the second amplifier to the second differential input during the first phase, and selectively coupling the output of the second amplifier to the fourth differential input during a second phase.

Abstract: A rail-rail comparator having an input stage with independent positive and negative differential voltage offset compensation tracks changes in Gm (transconductance) of the input stage. By tracking the changes in Gm (transconductance) of the input stage, hysteresis of the rail-rail comparator becomes insensitive to the input common mode voltage. A two-stage rail-rail comparator may be used for adding hysteresis to a second stage. The first stage of the two-stage rail-rail comparator operates at substantially unity gain. The second stage of the two-stage rail-rail comparator operates as a regular high gain amplifier with hysteresis. Additional circuitry tracks the Gm (transconductance) change of the first stage to make the second stage hysteresis insensitive to the input common mode voltage at the first stage. This also makes it easier to create a programmable hysteresis that is accurate over all input voltage values.

Abstract: An accurate temperature monitoring system that uses a precision current control circuit to apply accurately ratioed currents to a semiconductor device, which may be a bipolar junction transistor (BJT), used for sensing temperature. A change in base-emitter voltage (?VBE) proportional to the temperature of the BJT may be captured and provided to an ADC, which may generate a numeric value corresponding to that temperature. The precision current control circuit may be configured to generate a reference current, capture the base current of the BJT, generate a combined current equivalent to a sum total of the base current and a multiple of the reference current, and provide the combined current to the emitter of the BJT. In response to this combined current, the collector current of the BJT will be equivalent to the multiple of the reference current. The ratios of the various collector currents conducted by the BJT may thus be accurately controlled, leading to more accurate temperature measurements.

Abstract: An accurate temperature monitoring system that uses a precision current control circuit to apply accurately ratioed currents to a semiconductor device, which may be a bipolar junction transistor (BJT), used for sensing temperature. A change in base-emitter voltage (?VBE) proportional to the temperature of the BJT may be captured and provided to an ADC, which may generate a numeric value corresponding to that temperature. The precision current control circuit may be configured to generate a reference current, capture the base current of the BJT, generate a combined current equivalent to a sum total of the base current and a multiple of the reference current, and provide the combined current to the emitter of the BJT. In response to this combined current, the collector current of the BJT will be equivalent to the multiple of the reference current. The ratios of the various collector currents conducted by the BJT may thus be accurately controlled, leading to more accurate temperature measurements.

Abstract: In one set of embodiments the invention comprises a highly accurate, low-power, compact size DAC utilizing charge redistribution techniques. Two complementary conversions may be performed and added together to form a final DAC output voltage by performing charge redistribution a first time, and again a second time in a complementary fashion, followed by a summing of the two charge distributions, in effect canceling the odd order capacitor mismatch errors. By canceling all odd order mismatch errors the accuracy of the DAC may become a function of the square of the mismatch of the two capacitors, resulting in greatly increased accuracy. When performing the complementary conversions for multiple bits, the sequence in which each of the two capacitors is charged may be determined to minimize the even-order errors, especially second-order errors.

Abstract: A system and method for designing an integrated relaxation oscillator that exhibits reduced change in the frequency of oscillation caused by process variation. Improved sensitivity to component variation due to process shift is achieved through using more than one structure type when implementing the resistors affecting the RC time constant and threshold (trip point) voltages of the oscillator. Structure types are related to the fabrication process and for a CMOS process include, but are not limited to n-diffusion, p-diffusion, n-well, p-well, pinched n-well, pinched p-well, poly-silicon and metal. Each structure type exhibits statistically independent process variations, allowing for application of Lyapunov's extension of the Central Limit Theorem for statistically uncorrelated events to desensitize the effect from different possible causes. Thus, improvement in the performance of the oscillator may be achieved with a reduced trim requirement and without using external precision resistors.

Abstract: A system and method for designing an integrated relaxation oscillator that exhibits reduced change in the frequency of oscillation caused by process variation. Improved sensitivity to component variation due to process shift is achieved through using more than one structure type when implementing the resistors affecting the RC time constant and threshold (trip point) voltages of the oscillator. Structure types are related to the fabrication process and for a CMOS process include, but are not limited to n-diffusion, p-diffusion, n-well, p-well, pinched n-well, pinched p-well, poly-silicon and metal. Each structure type exhibits statistically independent process variations, allowing for application of Lyapunov's extension of the Central Limit Theorem for statistically uncorrelated events to desensitize the effect from different possible causes. Thus, improvement in the performance of the oscillator may be achieved with a reduced trim requirement and without using external precision resistors.