Patents by Inventor Aniruddha Dasgupta

Aniruddha Dasgupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240142515
    Abstract: An apparatus and method for efficiently managing power consumption of multiple partitions of an integrated circuit. A processing unit includes multiple partitions, each assigned to operation parameters of a respective power domain. Each of the partitions is assigned to operating parameters of a respective power domain. A power manager accesses a total power consumption budget for the multiple partitions and sends corresponding assigned power limits to the multiple partitions. A particular partition calculates a corresponding measurement of power consumption as a weighted sum of sampled signals, and performs steps to reduce power consumption when the particular partition determines the corresponding measurement of power consumption exceeds a corresponding assigned power limit. The power manager updates the assigned power limits within a first time interval.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: Amanullah Samit, Raman Madras Srinivasan, Aniruddha Dasgupta
  • Publication number: 20230273890
    Abstract: Systems, apparatuses, and methods for a host controller inferring idleness based on activity generated by a bus-attached peripheral device are disclosed. A host controller detects activity by a first device attached to the host controller via a first bus. The host controller generates an activity vector based on the detected activity, and the host controller determines whether the activity vector indicates that the first device is only engaging in handshaking or control activity rather than data transfer. If the first device is merely communicating status information, then the host controller infers idleness and conveys an idleness indicator to a power manager. The power manager turns off power to system memory and/or other components based on the idleness indicator, but keeps enough power on to allow the host controller to communicate with the first device for handshaking or status purposes.
    Type: Application
    Filed: February 28, 2022
    Publication date: August 31, 2023
    Inventors: Raul Gutierrez, Indrani Paul, Joseph Scanlon, Aniruddha Dasgupta, Madhusudan Chilakam
  • Patent number: 9904623
    Abstract: A system includes a functional unit, at least one cache coupled to the functional unit, and a power management unit coupled to the functional unit and the at least one cache, the power management unit configured to trigger the functional unit to initiate prefetching of data to repopulate the at least one cache prior to a predicted exit of the functional unit from an idle mode to an active mode. The system further may include a prediction unit to predict the exit from the idle mode for the functional unit as occurring a predetermined duration from an entry into the idle mode. The prediction unit may determine the predetermined duration based on a history of idle mode durations indicative of durations of previous instances in which the functional unit was in the idle mode.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: February 27, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Madhu Saravana Sibi Govindan, William Lloyd Bircher, Aniruddha Dasgupta, Dongyuan Zhan
  • Patent number: 9652019
    Abstract: A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes processing units each of which operates with respective operating parameters. Temperature sensors are included to measure a temperature of the one or more processing units during operation. A power manager determines a calculated power value independent of thermal conditions and current draw. The power manager reads each of a first thermal design power (TDP) value for the processing units and a second TDP value for a platform housing the semiconductor chip. The power manager determines a ratio of the first TDP value to the second TDP value. Additionally, the power manager determines another ratio of the first TDP value to the calculated power value. Using the measured temperature, the ratios and the calculated power value, the power manager determines a manner to adjust the operating parameters.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: May 16, 2017
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Praveen K. Dongara, Aniruddha Dasgupta, Adam Clark
  • Publication number: 20160321183
    Abstract: A system includes a functional unit, at least one cache coupled to the functional unit, and a power management unit coupled to the functional unit and the at least one cache, the power management unit configured to trigger the functional unit to initiate prefetching of data to repopulate the at least one cache prior to a predicted exit of the functional unit from an idle mode to an active mode. The system further may include a prediction unit to predict the exit from the idle mode for the functional unit as occurring a predetermined duration from an entry into the idle mode. The prediction unit may determine the predetermined duration based on a history of idle mode durations indicative of durations of previous instances in which the functional unit was in the idle mode.
    Type: Application
    Filed: May 1, 2015
    Publication date: November 3, 2016
    Inventors: Madhu Saravana Sibi Govindan, William Lloyd Bircher, Aniruddha Dasgupta, Dongyuan Zhan
  • Publication number: 20150346798
    Abstract: A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes processing units each of which operates with respective operating parameters. Temperature sensors are included to measure a temperature of the one or more processing units during operation. A power manager determines a calculated power value independent of thermal conditions and current draw. The power manager reads each of a first thermal design power (TDP) value for the processing units and a second TDP value for a platform housing the semiconductor chip. The power manager determines a ratio of the first TDP value to the second TDP value. Additionally, the power manager determines another ratio of the first TDP value to the calculated power value. Using the measured temperature, the ratios and the calculated power value, the power manager determines a manner to adjust the operating parameters.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 3, 2015
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Praveen K. Dongara, Aniruddha Dasgupta, Adam Clark