Abstract: A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults in the system is also disclosed.

Abstract: A backplane employed in a switch fabric, having the capability to allow signal communication between at least two modules. Two or more of the modules being adapted to employ different topologies from the following types of topologies: star, dual star, mesh, and cascaded mesh.

Abstract: A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults in the system is also disclosed.

Abstract: A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults in the system is also disclosed.

Abstract: A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults in the system is also disclosed.

Abstract: Embodiments of a topology for a backplane for a switch fabric and operation thereof are described.

Abstract: A memory controller apparatus and method for automatically detecting whether a particular memory unit location is unpopulated or populated with synchronous dynamic random access memories (DRAMs), or asynchronous fast page (FP) DRAMs or extended data out (EDO) DRAMs are disclosed. Logic in the memory controller detects a memory device type by writing a first data item to the memory device using at least a minimum common asynchronous memory write protocol meeting the write timing requirements of all asynchronous memory device types. An attempt is then made to read the first data from the memory device using a first asynchronous memory read protocol. If the first data is read from the memory device, the memory device is identified as being an asynchronous memory. If the first data is not read from the device, the memory control logic writes a second data item to the memory device using a synchronous memory write protocol.

Abstract: A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

Abstract: A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

Abstract: A memory controller having a data strobe that tracks the column access strobe signal in a computer system having Extended Data Out (EDO) DRAMs. The data strobe signal follows, by a predetermined delay, the column access strobe signal, and therefore any skew in the column access strobe signal is inherently included within the data strobe signal. As a result, the data can be latched out, responsive to said data strobe signal, at approximately the center of the valid window.

Abstract: An interrupt handling mechanism for converting PCI agent interrupts into interrupts compliant with a secondary bus standard interrupt protocol. PCI agent interrupts are processed by programmable logic for converting PCI compliant interrupts into, for example, ISA bus standard compliant interrupts for processing by a computer system which implements both a PCI bus and ISA bus. A programmable register provides for selecting which ISA interrupt will be generated by the programmable logic in response to a PCI agent interrupt.

Abstract: A bridge for coupling a host bus to a peripheral component interconnect (PCI) bus. A controller is used to transfer an address from the host bus while a datapath is used to transfer data from the host bus. The address and data is then transferred to the PCI bus over a set of signal lines coupled to the PCI bus such that each signal line transfers at least a portion of the address as well as at least a portion of data.

Abstract: Memory access control logic for controlling sequential and toggle mode burst accesses to a memory in a computer system using toggle mode automatic increment logic. The memory access control logic of the invention controls the sequence in which locations of a memory are accessed during a memory burst access operation wherein the burst access sequence is determined by an order in which a burst access starting address is incremented. Toggle increment logic for incrementing a starting address in a toggle sequence is included in the computer system in which the memory access control logic of the invention is used. An input bus receives a burst access request and a burst access starting address indicating a first memory location to be accessed in response to the burst access request from a device in the computer system. Additional logic determines whether the device requires a linear increment sequence or a toggle increment sequence for the burst access.

Abstract: A computer system is provided with a system memory unit comprising memory address and control signal generation circuitry, a number of banks of extended data out dynamic random access memory (EDODRAM), and a number of registers. The memory address and control signal generation circuitry generates memory addresses for the banks of EDODRAM, advantageously delivered over two address buses. The most significant bits (MSBs) of the memory addresses are buffered and delivered to the banks of EDODRAM over a first address bus, while the least significant bits (LSBs) of the memory addresses are "split" off and directly delivered, unbuffered, to the banks of EDODRAM over a second address bus to allow a column address to change at a faster rate by bypassing the buffer. Additionally, the memory address and control signal generation circuitry generates control signals for the banks of EDODRAM and the registers, including a column address strobe (CAS) signal with "shortened" active periods.

Abstract: A pulse width modulation circuit in a computer system for emulating a processor operating at a slower instruction execution speed. The pulse width modulator a computer system clock, and a register containing a first value. The first value is user-definable by software and specifies a proportion of time that a processor should remain idle. The apparatus further comprises a counter coupled to the clock, the counter having a range between a second and third values which includes the first value. A comparator is coupled to the counter and the register, and the comparator causes a central processing unit to suspend instruction execution for a specified interval of time. The comparator causes the central processing unit to resume instruction execution for remainder of the counter's range. The processor is therefore kept idle for proportions of time depending on the values of the register and the counter to emulate a slower speed processor.