Abstract: A memory controller and method are provided for controlling a memory device to process access requests issued by at least one master device, the memory device having a plurality of access regions. The memory controller has a pending access requests storage that buffers access requests that have been issued by a master device prior to those access requests being processed by the memory device. Access control circuitry then issues control commands to the plurality of access regions in order to control the memory device to process access requests retrieved from the pending access requests storage. A query structure is also provided that is configured to maintain, for each access region, information about the buffered access requests in the pending access requests storage, and the access control circuitry references the query structure when determining the control commands to be issued to the plurality of access regions.

Abstract: A data processing apparatus and method are provided for performing address translation in response to a memory access request issued by processing circuitry of the data processing apparatus and specifying a virtual address for a data item. Address translation circuitry performs an address translation process with reference to at least one descriptor provided by at least one page table, in order to produce a modified memory access request specifying a physical address for the data item. The address translation circuitry includes page table walk circuitry configured to generate at least one page table walk request in order to retrieve the at least one descriptor required for the address translation process. In addition, walk ahead circuitry is located in a path between the address translation circuitry and a memory device containing the at least one page table.

Abstract: A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.

Abstract: A data processing apparatus and method are provided for performing address translation in response to a memory access request issued by processing circuitry of the data processing apparatus and specifying a virtual address for a data item. Address translation circuitry performs an address translation process with reference to at least one descriptor provided by at least one page table, in order to produce a modified memory access request specifying a physical address for the data item. The address translation circuitry includes page table walk circuitry configured to generate at least one page table walk request in order to retrieve the at least one descriptor required for the address translation process. In addition, walk ahead circuitry is located in a path between the address translation circuitry and a memory device containing the at least one page table.

Abstract: An example system in accordance with an aspect of the present disclosure is to use local error detection (LED) and global error correction (GEC) information to check data fidelity and correct an error. The LED is to be calculated per cache line segment of data associated with a rank of a memory. Data fidelity may be checked in response to a memory read operation, based on the LED information, to identify a presence of an error and the location of the error among cache line segments of the rank. The cache line segment having the error may be corrected based on the GEC information, in response to identifying the error.

Abstract: The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.

Abstract: A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition the example apparatus includes a column decoder (606) to selectively activate a portion of the raw based on the column address and the signal asserted on the wordline.

Abstract: An example apparatus includes a row address register to store a row address corresponding to a row in a memory array. The example apparatus also includes a row decoder coupled to the row address register to assert a signal on a wordline of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.

Abstract: A data processing system utilising a descriptor ring 24 to facilitate communication between one or more general purpose processors 4, 6 and one or more devices 20, 22 employs a system memory management unit 18 for managing access by the devices 20, 22 to a main memory 16. The system memory management unit 18 uses address translation data for translating memory addresses generated by the devices 20, 22 into addresses supplied to the main memory 16. Prefetching circuitry 38 within the system memory management unit 18 serves to detect pointers read from the descriptor ring 24 and to prefetch address translation data into the translation lookaside buffer 30 of the system memory management unit 18.

Abstract: A memory controller and method are provided for controlling a memory device to process access requests issued by at least one master device, the memory device having a plurality of access regions. The memory controller has a pending access requests storage that buffers access requests that have been issued by a master device prior to those access requests being processed by the memory device. Access control circuitry then issues control commands to the plurality of access regions in order to control the memory device to process access requests retrieved from the pending access requests storage. A query structure is also provided that is configured to maintain, for each access region, information about the buffered access requests in the pending access requests storage, and the access control circuitry references the query structure when determining the control commands to be issued to the plurality of access regions.

Abstract: A system may use local error detection (LED) and global error correction (GEC) information to check data fidelity and correct an error. The LED may be calculated per cache line segment of data associated with a rank of a memory. Data fidelity may be checked in response to a memory read operation, based on the LED information, to identify a presence of an error and the location of the error among cache line segments of the rank. The cache line segment having the error may be corrected based on the GEC, in response to identifying the error.

Abstract: The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.

Abstract: An exemplary embodiment of the present invention may build data blocks in non-volatile memory. The corresponding parity blocks may be built in a fast, high endurance memory.