Abstract: A method, apparatus, and system are disclosed. In one embodiment the method detects a temperature event in a processor and then modifies the bus frequency of an I/O bus coupled to an I/O controller hub in response to the temperature event. In another embodiment, the apparatus includes a temperature detection unit that detects a temperature event in a processor and, additionally, a bus frequency modification unit that will modify the bus frequency of an I/O bus in response to the temperature event.

Abstract: A processor-based system may be operated in an effectively “always on” condition. The system may transition from a lower power consumption state to a higher power consumption state in response to the first operation of a power button. In response to a second operation of the power button, the system transitions from the higher power consumption state to the lower power consumption state. However, unless the system is unplugged, the system remains in a power consuming state even when the power button is repeatedly operated.

Abstract: A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of devices, and are accessible through the second bridge. A hub interface allows data to transfer downstream from the first bridge to the second bridge, and allows data to transfer upstream from the second bridge to the first bridge. A controller, external to the first and second bridges, accesses the configuration registers via the second bridge. A logic device allows the second bridge to send data to, and receive data from, the controller.

Abstract: In some embodiments, a method and apparatus for maintaining data integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are suspended, a parity error handler routine is invoked to perform parity error recovery according to stored transaction information regarding an error bus transaction of the detected parity error. In one embodiment, the stored information includes a bus master that caused the error, as well as an address associated with the corrupt data for which the parity error was asserted. In one embodiment, data logging is performed to track the bus masters associated with error bus transactions to enable identification of problematic or old hardware devices. Other embodiments are described and claims.

Abstract: Method and apparatus for supporting multi-function PCI devices in PCI bridges. Respective pre-fetch buffers are allocated in response to respective initial data transfer requests issued by a multi-function PCI device. A programmable buffer fill watermark is set up for each pre-fetch buffer. While a portion of data corresponding to the data transfer requests fill the pre-fetch buffers, the fill level of each buffer is monitored to determine if it meets or exceeds its buffer fill watermark. In response to such a condition, the multi-function PCI device is connected to the PCI bridge and a virtual buffer is mapped to the pre-fetch buffer. The pre-fetch buffer is then emptied. During subsequent data transfers, each of the pre-fetch buffer becomes filled, the PCI device is connected, and the virtual buffer is mapped to the filled buffer. The process is continued until all data corresponding to the original data transfer request is received by the multi-function PCI device.

Abstract: A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of devices, and are accessible through the second bridge. A hub interface allows data to transfer downstream from the first bridge to the second bridge, and allows data to transfer upstream from the second bridge to the first bridge. A controller, external to the first and second bridges, accesses the configuration registers via the second bridge. A logic device allows the second bridge to send data to, and receive data from, the controller.

Abstract: Embodiments of the present invention provide a method and apparatus to allow an I/O controller to alert an external controller using an enhanced SMBus implementation that enables bi-directional capability on SMBALERT#. I/O controller includes an auxiliary control register and alert output enable (AOEN) register. When host sets AOE bit in auxiliary control register, SMBALERT# signal is configured as an output signal with bi-directional functionality. External controller uses an interface command to write to AOEN register and determine events/conditions it wants to be alerted on. SMBALERT# is activated in response to a detected event/condition. In response to SMBALERT#, external controller determines the alert generation condition using byte read commands on the system management bus, and clears SMBALERT#.

Abstract: Access to internal configuration registers on a computer system's chipset using an external micro-controller is provided. A SMB configuration read command including a register address may be received from an external micro-controller. Access to an internal bus may be requested from a bus arbiter. If internal bus access is granted, the SMB configuration read command may be forwarded to a device including the identified register address using the internal bus. In response to the SMB configuration read command, configuration register values from the device may be received. The configuration register values may be forwarded to the external micro-controller.

Abstract: Embodiments of the present invention provide a system event log for a computer system. The system event log may comprise a RAM coupled to a system bus. The system event log may be configured to record information in the RAM corresponding to bus transactions on the system bus. The information may be used to de-bug system problems.

Abstract: The present invention relates to a system and method to implement a cost-effective remote system management mechanism using a serial communication controller and interrupts. The system includes a requesting device operatively coupled to a network to send a status query through a serial port in the requesting device. The system further includes a responding device operatively coupled to the network to receive the status query from the requesting device. The status query inquires about operational status of the responding device. The responding device receives the status query through a serial port in the responding device, processes the status query, and reports the operational status through the serial port in the responding device to the requesting device in response to the status query sent by the requesting device.

Abstract: According to one embodiment of the invention, a first signal line is provided for a serial interface unit (SIU) of an I/O controller to report interrupt requests to an interrupt controller. In one embodiment, a transition of the first signal line from a first level (e.g., low level or logic 0) to a second level (e.g., high level or logic 1) indicates a pending interrupt to the interrupt controller. A pull up resistor is provided to pull the first signal line to the second level when the first signal line is not driven by the SIU. In response to detecting an interrupt request initiated by an I/O device, a transition from the first level to the second level is generated on the first signal line for a predetermined duration to report the pending interrupt request to the interrupt controller.

Abstract: The present invention relates to a system and method to implement a cost-effective remote system management mechanism using a serial communication controller and interrupts. The system includes a requesting device operatively coupled to a network to send a status query through a serial port in the requesting device. The system further includes a responding device operatively coupled to the network to receive the status query from the requesting device. The status query inquires about operational status of the responding device. The responding device receives the status query through a serial port in the responding device, processes the status query, and reports the operational status through the serial port in the responding device to the requesting device in response to the status query sent by the requesting device.

Abstract: The present invention relates to a system and method to configure input/output (SIO) devices to use selected pairs of port addresses. The method includes writing a first unique value to a selected port address. The method further includes writing a second unique value to the selected port address. The method also includes performing a read operation on the selected port address to obtain a read value. The method additionally includes setting an input/output (IO) device to use the selected port address.

Abstract: Embodiments of the present invention provide a method and apparatus to allow an I/O controller to alert an external controller using an enhanced SMBus implementation that enables bi-directional capability on SMBALERT#. I/O controller includes an auxiliary control register and alert output enable (AOEN) register. When host sets AOE bit in auxiliary control register, SMBALERT# signal is configured as an output signal with bi-directional functionality. External controller uses an interface command to write to AOEN register and determine events/conditions it wants to be alerted on. SMBALERT# is activated in response to a detected event/condition. In response to SMBALERT#, external controller determines the alert generation condition using byte read commands on the system management bus, and clears SMBALERT#.

Abstract: Embodiments of the present invention provide a method and apparatus for implementing fault detection and correction in a computer network. In one embodiment, the invention may provides a multi-stage watch-dog timer to monitor device operation in a computer system. A system bus controller may receive data related to a computer system fault from the multi-stage watch-dog timer and may log the fault data in memory. The system bus controller may also forward the fault data to an external server. In an alternative embodiment, the invention provides a processor that may re-set the multi-stage watch-dog timer at pre-determined intervals during normal operation. In yet another alternative embodiment, the processor may receive an interrupt from the watch-dog timer if at least one stage of the multi-stage watch-dog timer is not re-set during the fault and the processor may further run a diagnostic test to find the fault.

Abstract: Embodiments of the present invention relate to providing system management and control of chipset modules using an external micro controller. In an embodiment of the present invention, a SMB buffer read command including a buffer address may be received from an external micro-controller. Internal bus access may be requested from a bus arbiter. If bus access is granted, the SMB buffer read command may be sent to a module identified by the buffer address. The module is at least one of a plurality of modules having an associated data buffer to log data related to the operation of the module. The contents of the data buffer associated with the module may be received and forwarded to the external micro-controller.

Abstract: Embodiments of the present invention provide a system event log for a computer system. The system event log may comprise a RAM coupled to a system bus. The system event log may be configured to record information in the RAM corresponding to bus transactions on the system bus. The information may be used to de-bug system problems.

Abstract: Access to internal configuration registers on a computer system's chipset using an external micro-controller is provided. A SMB configuration read command including a register address may be received from an external micro-controller. Access to an internal bus may be requested from a bus arbiter. If internal bus access is granted, the SMB configuration read command may be forwarded to a device including the identified register address using the internal bus. In response to the SMB configuration read command, configuration register values from the device may be received. The configuration register values may be forwarded to the external micro-controller.

Abstract: According to one embodiment of the invention, a first signal line is provided for a serial interface unit (SIU) of an I/O controller to report interrupt requests to an interrupt controller. In one embodiment, a transition of the first signal line from a first level (e.g., low level or logic 0) to a second level (e.g., high level or logic 1) indicates a pending interrupt to the interrupt controller. A pull up resistor is provided to pull the first signal line to the second level when the first signal line is not driven by the SIU. In response to detecting an interrupt request initiated by an I/O device, a transition from the first level to the second level is generated on the first signal line for a predetermined duration to report the pending interrupt request to the interrupt controller.

Abstract: Alpha values associated with video mixing operations are sent to a memory on a low pin count bus. The memory is accessible to a video mixer, which retrieves the alpha values to perform a mixing operation. The alpha values for a field are sent to the memory during the field time for a previous field rather than during the vertical blanking interval. The alpha values may be compressed prior to transmission.