Abstract: In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector instruction is of a first width and the vector execution unit is of a smaller width. The processor further includes a control logic coupled to the vector execution unit to compress a number of execution cycles consumed in execution of the vector instruction when at least some of the individual data elements are not to be operated on by the vector instruction. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector instruction is of a first width and the vector execution unit is of a smaller width. The processor further includes a control logic coupled to the vector execution unit to compress a number of execution cycles consumed in execution of the vector instruction when at least some of the individual data elements are not to be operated on by the vector instruction. Other embodiments are described and claimed.

Abstract: A method and apparatus for hierarchical routing in mesh systems. The method may include splitting 420 a mesh network of nodes into a plurality of partitions, each partition including at least one node, dividing 430 a first partition into a plurality of rectangular regions, determining 440 a partition route from a source region to a destination region of the plurality of rectangular regions, and providing 450 a region route from a source node within one of the plurality of rectangular regions to a destination node within the same rectangular region. The method may also include routing 460 a packet from a source node within the source region to a destination node within the destination region using the partition route and the region route.