Abstract: A system and method, for reprogramming registers without having to reprogram unchanged registers. The registers are divided into groups based on common characteristics or functions. The values for the groups that differ from the current values are written into a linked list, which is then loaded into the appropriate registers. The linked list contains information indicating the groups of registers in the linked list.

Abstract: Presented herein is a unified decoder architecture. A system comprises a video decoder, instruction memory, and a host processor. The video decoder decodes the video data encoded with the particular standard. The instruction memory stores a first set of instructions and a second set of instructions. The first set of instructions are for decoding encoded video data according to a first encoding standard. The second set of instruction are for decoding encoded video data according to a second encoding standard. The host processor provides an indication to the video decoder indicating the particular encoding standard. The video decoder executes the first set of instructions if the indication indicates that the particular encoding standard is the first encoding standard and executes the second set of instructions if the indication indicates that the particular encoding standard is the second encoding standard.

Abstract: Systems and methods for decoding of digital video standard material during variable length decoding are disclosed. In one embodiment, a method in accordance with the present invention may comprise, for example, receiving a first portion of encoded video data stream and a second portion of encoded video data stream, wherein the first portion and the second portion are parts of one encoded symbol in an encoded video data stream; generating a concatenated video data stream comprising the first portion and the second portion; and decoding the concatenated video data stream.

Abstract: A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases using the code memory, the processor signals a direct memory access (DMA) module to transfer a new code portion to the code memory. The DMA module transfers the new code portion to the code memory and transmits a signal to the processor when the transfer is completed. The signal causes the processor to resume. When the processor resumes, the processor begins executing the instructions at the next code address.

Abstract: A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases using the code memory, the processor signals a direct memory access (DMA) module to transfer a new code portion to the code memory. The DMA module transfers the new code portion to the code memory and transmits a signal to the processor when the transfer is completed. The signal causes the processor to resume. When the processor resumes, the processor begins executing the instructions at the next code address.

Abstract: A system, method, and apparatus for dividing and truncating a dividend by a divisor, wherein the magnitude of the divisor is a positive power of two, e.g., 2x, is presented herein. If the divisor is positive, the sign bit of the dividend is concatenated x times and added to the dividend. If the divisor is negative, the dividend is inverted, the sign bit of the inverted dividend is concatenated x times, and added to the inverted dividend. The sign bit of the divisor is also added to the sum and the result is right shifted x times. If the signs of the divisor and the dividend are the same, a zero is shifted into the most significant bit during each right shift. If the signs of the divisor and the dividend are different, the most-significant-bit (sign bit) of the result of addition is shifted into the most significant bit during each right shift.

Abstract: A system, method, and apparatus for efficient rounding of signed numbers is presented herein. If the divisor is positive, the dividend is added to one half of the magnitude of the divisor. If the divisor is negative, the complement of the dividend is added to one half of the magnitude of the divisor. If the dividend is negative, and the divisor is also negative, one is added to the sum of the inverted dividend and one-half of the magnitude of the divisor. If the dividend is negative and the divisor is positive, one is subtracted from the sum of the dividend and one-half the magnitude of the divisor. The result is then right shifted x times. If the signs of the divisor and dividend are different, a most-significant-bit(sign-bit) of the result is shifted in as the most significant bit during each right shift. Otherwise, a “0” is shifted in.

Abstract: Presented herein is a system, method, and apparatus for decoding variable length codes. In one embodiment, there is presented a method for decoding variable length coded symbols. The method comprises storing one or more symbols from a plurality of variable length coded symbols in a first register; storing a portion of a particular symbol from the plurality of variable length coded symbols in the first register; storing another portion of the particular symbol in a second register; and storing the contents of the first register in memory after storing the portion of the particular symbol in the first register.

Abstract: A system and method, for reprogramming registers without having to reprogram unchanged registers. The registers are divided into groups based on common characteristics or functions. The values for the groups that differ from the current values are written into a linked list, which is then loaded into the appropriate registers. The linked list contains information indicating the groups of registers in the linked list.

Abstract: Presented herein is a unified decoder architecture. A system comprises a video decoder, instruction memory, and a host processor. The video decoder decodes the video data encoded with the particular standard. The instruction memory stores a first set of instructions and a second set of instructions. The first set of instructions are for decoding encoded video data according to a first encoding standard. The second set of instruction are for decoding encoded video data according to a second encoding standard. The host processor provides an indication to the video decoder indicating the particular encoding standard. The video decoder executes the first set of instructions if the indication indicates that the particular encoding standard is the first encoding standard and executes the second set of instructions if the indication indicates that the particular encoding standard is the second encoding standard.

Abstract: Systems and methods for decoding of digital video standard material during variable length decoding are disclosed. In one embodiment, a method in accordance with the present invention may comprise, for example, receiving a first portion of encoded video data stream and a second portion of encoded video data stream, wherein the first portion and the second portion are parts of one encoded symbol in an encoded video data stream; generating a concatenated video data stream comprising the first portion and the second portion; and decoding the concatenated video data stream.

Abstract: Presented herein is a system, method, and apparatus for decoding variable length codes. In one embodiment, there is presented a method for a method for decoding variable length coded symbols. The method comprises storing one or more symbols from a plurality of variable length coded symbols in a first register; storing a portion of a particular symbol from the plurality of variable length coded symbols in the first register; storing another portion of the particular symbol in a second register; and storing the contents of the first register in memory after storing the portion of the particular symbol in the first register.

Abstract: A system method, and apparatus for decoding a bitstream comprising variable length coded symbols are presented herein. The bitstream is parsed and the symbols that are decoded are extracted from the bitstream. The symbols that are not decoded in the parse are stored in a register. When the register is full, the contents therein are stored in the next available data word in the memory. In the foregoing manner, the bitstream without the decoded symbols is stored continuously in memory, even where the width of the memory is substantially wider than the variable length symbols.

Abstract: A system, method, and apparatus for decoding a bitstream comprising variable length coded symbols are presented herein. The bitstream is parsed and the symbols that are decoded are extracted from the bitstream. The symbols that are not decoded in the parse are stored in a register. When the register is full, the contents therein are stored in the next available data word in the memory. In the foregoing manner, the bitstream without the decoded symbols is stored continuously in memory, even where the width of the memory is substantially wider than the variable length symbols.

Abstract: A system, method, and apparatus for dividing and truncating a dividend by a divisor, wherein the magnitude of the divisor is a positive power of two, e.g., 2x, is presented herein. If the divisor is positive, the sign bit of the dividend is concatenated x times and added to the dividend. If the divisor is negative, the dividend is inverted, the sign bit of the inverted dividend is concatenated x times, and added to the inverted dividend. The sign bit of the divisor is also added to the sum and the result is right shifted x times. If the signs of the divisor and the dividend are the same, a zero is shifted into the most significant bit during each right shift. If the signs of the divisor and the dividend are different, the most-significant-bit (sign bit) of the result of addition is shifted into the most significant bit during each right shift.

Abstract: A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases using the code memory, the processor signals a direct memory access (DMA) module to transfer a new code portion to the code memory. The DMA module transfers the new code portion to the code memory and transmits a signal to the processor when the transfer is completed. The signal causes the processor to resume. When the processor resumes, the processor begins executing the instructions at the next code address.

Abstract: A system, method, and apparatus for efficient rounding of signed numbers is presented herein. If the divisor is positive, the dividend is added to one half of the magnitude of the divisor. If the divisor is negative, the complement of the dividend is added to one half of the magnitude of the divisor. If the dividend is negative, and the divisor is also negative, one is added to the sum of the inverted dividend and one-half of the magnitude of the divisor. If the dividend is negative and the divisor is positive, one is subtracted from the sum of the dividend and one-half the magnitude of the divisor. The result is then right shifted x times. If the signs of the divisor and dividend are different, a most-significant-bit(sign-bit) of the result is shifted in as the most significant bit during each right shift. Otherwise, a “0” is shifted in.