Patents by Inventor ANIRUDH KADIYALA
ANIRUDH KADIYALA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9903913Abstract: A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.Type: GrantFiled: January 20, 2014Date of Patent: February 27, 2018Assignee: Advanced Micro Devices, Inc.Inventors: Atchyuth Gorti, Anirudh Kadiyala, Bill K. C. Kwan, Venkat Kuchipudi
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Patent number: 9740234Abstract: An on-chip clock controller includes a primary clock gating cell and a secondary clock gating cell. The primary clock gating cell includes a first clock input terminal coupled to receive an input clock signal and a first enable input terminal coupled to receive an enable signal. The primary clock gating cell also include a first clock output terminal configured to generate a first output clock signal based at least in part on the input clock signal and the enable signal. The secondary clock gating includes a second clock input terminal coupled to receive the input clock signal and a second clock output terminal configured to generate a second output clock signal based at least in part on the input clock signal. The enable signal is based at least in part on the second output clock signal.Type: GrantFiled: March 31, 2016Date of Patent: August 22, 2017Assignee: QUALCOMM IncorporatedInventors: Hong Kim, Paul Policke, Anirudh Kadiyala
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Publication number: 20140359386Abstract: A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.Type: ApplicationFiled: January 20, 2014Publication date: December 4, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Atchyuth Gorti, Anirudh Kadiyala, Bill K.C. Kwan, Venkat Krishna Kuchipudi
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Publication number: 20140181602Abstract: A method includes receiving in a computing apparatus a model of an integrated circuit device including a memory array. The memory array is modeled as a plurality of device primitives. A test pattern analysis of the memory array is performed using the model in the computing apparatus. A system includes a memory array modeling unit and a test pattern analysis unit. The memory array modeling unit is operable to generate a model of an integrated circuit device including an memory array. The memory array is modeled as a plurality of device primitives. The test pattern analysis unit is operable to performing a test pattern analysis of the memory array using the model in the computing apparatus.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Vibhor Mittal, Anirudh Kadiyala
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Patent number: 8694842Abstract: A method, computer program storage device and apparatus are provided for flexible observability during a scan. In one aspect of the present invention, a method is provided. The method includes providing a selector load input to at least a portion of a scan chain, selecting an observe-only scan mode for the at least a portion of the scan chain based at least upon the selector load input, and providing a data input to a storage element in the scan chain based at least upon the observe-only scan mode. The apparatus includes a first scan chain multiplexor comprising a selector input, a first input terminal, a second input terminal and an output terminal. The apparatus also includes a first scan chain storage element comprising an input terminal and an output terminal, where the input terminal of the first scan chain storage element is communicatively coupled to the output terminal of the first scan chain multiplexor.Type: GrantFiled: November 17, 2010Date of Patent: April 8, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Atchyuth K. Gorti, Anirudh Kadiyala, Aditya Jagirdar
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Patent number: 8633725Abstract: A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.Type: GrantFiled: September 10, 2010Date of Patent: January 21, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Atchyuth K. Gorti, Anirudh Kadiyala, Bill K. Kwan, Venkat K Kuchipudi
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Publication number: 20120124434Abstract: A method, computer program storage device and apparatus are provided for flexible observability during a scan. In one aspect of the present invention, a method is provided. The method includes providing a selector load input to at least a portion of a scan chain, selecting an observe-only scan mode for the at least a portion of the scan chain based at least upon the selector load input, and providing a data input to a storage element in the scan chain based at least upon the observe-only scan mode. The apparatus includes a first scan chain multiplexor comprising a selector input, a first input terminal, a second input terminal and an output terminal. The apparatus also includes a first scan chain storage element comprising an input terminal and an output terminal, where the input terminal of the first scan chain storage element is communicatively coupled to the output terminal of the first scan chain multiplexor.Type: ApplicationFiled: November 17, 2010Publication date: May 17, 2012Inventors: Atchyuth K. Gorti, Anirudh Kadiyala, Aditya Jagirdar
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Publication number: 20120062266Abstract: A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.Type: ApplicationFiled: September 10, 2010Publication date: March 15, 2012Inventors: ATCHYUTH K. GORTI, ANIRUDH KADIYALA, BILL K. KWAN, VENKAT K. KUCHIPUDI