Abstract: An image sensor may include an array of imaging pixels and verification circuitry. Row control circuitry including row drivers may provide control signals to the pixels in the array of imaging pixels. The verification circuitry may test proper operation of the row drivers. The verification circuitry be configured to pre-charge the first and second storage capacitors to a first bias voltage, intentionally discharge the first and second storage capacitors to a second bias voltage, reset only the first storage capacitor back to the first bias voltage, and use a first sample from the first storage capacitor and a second sample from the second storage capacitor to test operation of the row driver. If the row driver is operating correctly, a voltage swing will be detected between the two samples. If the row driver is stuck high or stuck low, the first and second samples may be the same.

Abstract: An image sensor may include an array of imaging pixels and verification circuitry. Row control circuitry including row drivers may provide control signals to the pixels in the array of imaging pixels. The verification circuitry may test proper operation of the row drivers. The verification circuitry be configured to pre-charge the first and second storage capacitors to a first bias voltage, intentionally discharge the first and second storage capacitors to a second bias voltage, reset only the first storage capacitor back to the first bias voltage, and use a first sample from the first storage capacitor and a second sample from the second storage capacitor to test operation of the row driver. If the row driver is operating correctly, a voltage swing will be detected between the two samples. If the row driver is stuck high or stuck low, the first and second samples may be the same.

Abstract: An image sensor may include an array of imaging pixels and row control circuitry. Each imaging pixel may include a photodiode, a floating diffusion region, a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region, a dual conversion gain transistor coupled to the floating diffusion region, and a storage capacitor coupled to the dual conversion gain transistor. The capacitor may have a plate that receives a modulated control signal and the row control circuitry may be configured to modulate the control signal. To reduce image artifacts, the modulated control signal may be modulated low during the integration time of the pixel and may be modulated high during the high conversion gain readout time of the pixel.

Abstract: An image sensor may include an array of imaging pixels and row control circuitry. Each imaging pixel may include a photodiode, a floating diffusion region, a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region, a dual conversion gain transistor coupled to the floating diffusion region, and a storage capacitor coupled to the dual conversion gain transistor. The capacitor may have a plate that receives a modulated control signal and the row control circuitry may be configured to modulate the control signal. To reduce image artifacts, the modulated control signal may be modulated low during the integration time of the pixel and may be modulated high during the high conversion gain readout time of the pixel.

Abstract: Diode string configurations are provided that employ one or more guard bars (GBARS) positioned adjacent an end diode structure of a diode string to create a parasitic silicon-controlled rectifier (SCR) coupling between the end diode structure and the guard bar/s that operates to discharge current of an ESD event through a lateral parasitic bipolar transistor of the SCR and away from the individual diodes of the diode string. One or more of the disclosed guard bars may be positioned adjacent to a diode on a first end of a diode string to create a lateral SCR coupling for ESD discharge away from all of the diodes in the diode string without requiring positioning of a last diode on an opposite end of the same diode string adjacent the first terminal diode.

Abstract: Diode circuit layout topologies and methods are disclosed that exhibit reduced lateral parasitic bipolar characteristics at lateral parasitic bipolar circuit emitter edges during ESD or other voltage events as compared to conventional circuit layout topologies. The disclosed diode circuit layout topologies may be implemented to recess parasitic emitter ends relative to surrounding well ties, for example, to reduce or substantially eliminate parasitic bipolar action at lateral emitter edges of the circuitry during ESD events so as to provide higher current threshold for device failure, allowing for smaller device area and/or improved ESD robustness for a given circuit device.

Abstract: Diode circuit layout topologies and methods are disclosed that exhibit reduced lateral parasitic bipolar characteristics at lateral parasitic bipolar circuit emitter edges during ESD or other voltage events as compared to conventional circuit layout topologies. The disclosed diode circuit layout topologies may be implemented to recess parasitic emitter ends relative to surrounding well ties, for example, to reduce or substantially eliminate parasitic bipolar action at lateral emitter edges of the circuitry during ESD events so as to provide higher current threshold for device failure, allowing for smaller device area and/or improved ESD robustness for a given circuit device.

Abstract: A chip-on-glass (COG) display driver comprises a direct current to direct current converter (DC-DC) converter that uses “off-glass” and/or “off-chip” inductive/capacitive (LC) components. The DC-DC converter can be configured to use either an internal or external switch (such as a power FET) in response to a mode signal. Selection of an internal or external mode allows a single converter chip design to be optimized for various applications.