Patents by Inventor Anirudha KULKARNI

Anirudha KULKARNI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS AND SYSTEMS FOR USE IN PROCESSING SEEDS
    Publication number: 20240034503
    Abstract: Systems and methods for filling cassettes consistent with sets of seeds are provided. One example computer-implemented method includes, in response to a request for a schedule to fill a plurality of the cassettes, accessing data associated with the cassettes including a seed set specific to each of the cassettes and generating a schedule to fill the plurality of cassettes with seeds, consistent with the seed sets specific to the plurality of cassettes, via a gantry, multiple counting stations, and a filling station, based on a throughput of the gantry, the multiple counting stations, and the filling station. The method then includes executing the schedule at the gantry, the multiple counting stations, and the filling station to fill at least a portion of the plurality of cassettes with the appropriate sets of seeds consistent with the schedule.
    Type: Application
    Filed: July 20, 2023
    Publication date: February 1, 2024
    Inventors: Dave BAITINGER, Jennifer BECKER, Thomas EMBORG, Scott GRASMAN, Chung-Hsuan HUANG, Shrikant JARUGUMILLI, Anirudha KULKARNI, Krishna NANDANOOR, Barrett THOMAS, Eric THOMPSON
  • Circuit for testing integrated circuits
    Patent number: 9689924
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 27, 2017
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Anirudha Kulkarni, Jasvir Singh
  • Circuit for testing integrated circuits
    Patent number: 9632140
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: April 25, 2017
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Anirudha Kulkarni, Jasvir Singh
  • CIRCUIT FOR TESTING INTEGRATED CIRCUITS
    Publication number: 20160131705
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Application
    Filed: December 28, 2015
    Publication date: May 12, 2016
    Inventors: ANIRUDHA KULKARNI, JASVIR SINGH
  • CIRCUIT FOR TESTING INTEGRATED CIRCUITS
    Publication number: 20150106672
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Anirudha Kulkarni, JASVIR SINGH
  • Circuit for testing integrated circuits
    Patent number: 8918689
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: December 23, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Anirudha Kulkarni, Jasvir Singh
  • CIRCUIT FOR TESTING INTEGRATED CIRCUITS
    Publication number: 20120017130
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Application
    Filed: August 30, 2010
    Publication date: January 19, 2012
    Applicant: STMICROELECTRONICS Pvt. Ltd.
    Inventors: Anirudha KULKARNI, Jasvir Singh