Abstract: A device for error correction and methods thereof are disclosed. The method includes retrieving raw data from a memory device during a first operational phase of the error correction device. The raw data is retrieved by a bus interface device that interfaces with a variety of memory devices. During a second operational phase, the raw data is outputted from the bus interface device to the bus master. In addition, error correction data is calculated, and error correction is performed on the raw data during the second operational phase. By retrieving the raw data before performing error correction, and by outputting the raw data and correction the raw data during the same operational phase, data may be retrieved from the memory more rapidly.

Abstract: A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time. The method further includes receiving an input signal at an input of a first latch of the circuit device and receiving an output signal at an input of a second latch of the circuit device. The method additionally includes delaying a clock signal by a first delay to provide a first adjusted clock signal and delaying the clock signal by a second delay to provide a second adjusted clock signal. In one embodiment, the first delay and the second delay are based on the first operational characteristic. The method further includes latching the input signal at the first latch responsive to the first adjusted clock signal and latching the output signal at the second latch responsive to the second adjusted clock signal.

Abstract: A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed to reduce a current needed from the clock driver to drive the plurality of synchronous cells.

Abstract: An integrated circuit comprises a volatile memory array, a non-volatile memory array, a plurality of registers, and a plurality of flip-flops. A portion of the non-volatile memory array is used for storing an address of a defective memory cell of the volatile memory array. The plurality of registers is coupled to the non-volatile memory array. The plurality of registers temporarily stores the address of the defective memory cell during a normal operating mode of the integrated circuit. Each of the plurality of flip-flops are used for substituting for a defective memory cell of the volatile memory array and are implemented on the integrated circuit physically separate from the volatile memory array.