Patents by Inventor Anisul Khan
Anisul Khan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9236255Abstract: In some embodiments, a method of forming a three dimensional NAND structure atop a substrate may include providing to a process chamber a substrate having alternating nitride layers and oxide layers or alternating polycrystalline silicon layers and oxide layers formed atop the substrate and a photoresist layer formed atop the alternating layers; etching the photoresist layer to expose at least a portion of the alternating nitride layers and oxide layers or alternating polycrystalline silicon layers and oxide layers; providing a process gas comprising sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), and oxygen (O2) to the process chamber; providing an RF power of about 4 kW to about 6 kW to an RF coil to ignite the process gas to form a plasma; and etching through a desired number of the alternating layers to form a feature of a NAND structure.Type: GrantFiled: June 24, 2014Date of Patent: January 12, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Sang Wook Kim, Han Soo Cho, Joo Won Han, Kee Young Cho, Kuan-Ting Liu, Anisul Khan
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Patent number: 8956500Abstract: An inductively-coupled plasma processing chamber has a chamber with a ceiling. A first and second antenna are placed adjacent to the ceiling. The first antenna is concentric to the second antenna. A plasma source power supply is coupled to the first and second antenna. The plasma source power supply generates a first RF power to the first antenna, and a second RF power to the second antenna. A substrate support disposed within the chamber. The size of the first antenna and a distance between the substrate support are such that the etch rate of the substrate on the substrate support is substantially uniform.Type: GrantFiled: April 24, 2007Date of Patent: February 17, 2015Assignee: Applied Materials, Inc.Inventors: Stephen Yuen, Kyeong-Tae Lee, Valentin Todorow, Tae Won Kim, Anisul Khan, Shashank Deshmukh
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Publication number: 20150004796Abstract: In some embodiments, a method of forming a three dimensional NAND structure atop a substrate may include providing to a process chamber a substrate having alternating nitride layers and oxide layers or alternating polycrystalline silicon layers and oxide layers formed atop the substrate and a photoresist layer formed atop the alternating layers; etching the photoresist layer to expose at least a portion of the alternating nitride layers and oxide layers or alternating polycrystalline silicon layers and oxide layers; providing a process gas comprising sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), and oxygen (O2) to the process chamber; providing an RF power of about 4 kW to about 6 kW to an RF coil to ignite the process gas to form a plasma; and etching through a desired number of the alternating layers to form a feature of a NAND structure.Type: ApplicationFiled: June 24, 2014Publication date: January 1, 2015Inventors: SANG WOOK KIM, HAN SOO CHO, JOO WON HAN, KEE YOUNG CHO, KUAN-TING LIU, ANISUL KHAN
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Patent number: 8231736Abstract: A cleaning process for recovering an anodized aluminum part is particularly useful when the part has been exposed to a fluorine-containing plasma in etch reactor. The part is bathed in an agitated solution of a fluoride acid, such as ammonium fluoride, which converts aluminum fluoride to a soluble fluoride. The part is rinsed in water. The pores of the cleaned anodization may be resealed by a submerging the part in hot agitated deionized water.Type: GrantFiled: August 27, 2007Date of Patent: July 31, 2012Assignee: Applied Materials, Inc.Inventors: Jennifer Y. Sun, Senh Thach, Xi Zhu, Li Xu, Anisul Khan
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Patent number: 8133817Abstract: Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.Type: GrantFiled: November 30, 2008Date of Patent: March 13, 2012Assignee: Applied Materials, Inc.Inventors: Hiroki Sasano, Meihua Shen, Radhika Mani, Sunil Srinivasan, Daehee Weon, Nicolas Gani, Shashank Deshmukh, Anisul Khan
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Publication number: 20090170333Abstract: Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.Type: ApplicationFiled: November 30, 2008Publication date: July 2, 2009Inventors: Hiroki Sasano, Meihua Shen, Radhika Mani, Sunil Srinivasan, Daehee Weon, Nicolas Gani, Shashank Deshmukh, Anisul Khan
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Publication number: 20090056745Abstract: A cleaning process for recovering an anodized aluminum part is particularly useful when the part has been exposed to a fluorine-containing plasma in etch reactor. The part is bathed in an agitated solution of a fluoride acid, such as ammonium fluoride, which converts aluminum fluoride to a soluble fluoride. The part is rinsed in water. The pores of the cleaned anodization may be resealed by a submerging the part in hot agitated deionized water.Type: ApplicationFiled: August 27, 2007Publication date: March 5, 2009Applicant: Applied Materials, Inc.Inventors: JENNIFER Y. SUN, Senh Thach, Xi Zhu, Li Xu, Anisul Khan
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Publication number: 20080264904Abstract: An inductively-coupled plasma processing chamber has a chamber with a ceiling. A first and second antenna are placed adjacent to the ceiling. The first antenna is concentric to the second antenna. A plasma source power supply is coupled to the first and second antenna. The plasma source power supply generates a first RF power to the first antenna, and a second RF power to the second antenna. A substrate support disposed within the chamber. The size of the first antenna and a distance between the substrate support are such that the etch rate of the substrate on the substrate support is substantially uniform.Type: ApplicationFiled: April 24, 2007Publication date: October 30, 2008Inventors: STEPHEN YUEN, Kyeong-Tae Lee, Valentin Todorow, Tae Won Kim, Anisul Khan, Shashank Deshmukh
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Publication number: 20060032833Abstract: A method of etching is provided that includes transferring a substrate into a vacuum environment, etching a material layer on the substrate and depositing a polymeric film encapsulating etch residues on the substrate without removing the substrate from the vacuum environment.Type: ApplicationFiled: August 10, 2004Publication date: February 16, 2006Inventors: Mark Kawaguchi, Thorsten Lill, Anisul Khan
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Patent number: 6979652Abstract: Openings of variable shape are made sequentially by alternately etching an opening in silicon and depositing a conformal fluorocarbon polymer on the sidewalls. This polymer protects the sidewalls of the opening from further etching. An isotropic etch can be carried out to change the profile of the etched feature, and for lift-off of the etched feature from the silicon substrate.Type: GrantFiled: April 8, 2002Date of Patent: December 27, 2005Assignee: Applied Materials, Inc.Inventors: Anisul Khan, Sharma V Pamarthy, Sanjay Thekdi, Ajay Kumar
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Patent number: 6954561Abstract: Thermo-optic devices including a bottom cladding layer, a patterned core material and a top cladding layer, each having a different refractive index, can be made by depositing a heater material, such as tungsten or chromium, on the outside of the bottom and/or top cladding layer. Depending on the refractive index differences between the cladding layers and the core layers, the amount of heater material can also be varied. The heater material can surround the cladding layers, can be present on the sidewalls and top only, or the sidewalls alone, to provide sufficient heat to change the refractive index of the layers and thus the path of light passing-through the device. These devices when built into the substrate can be connected to underlying devices for vertical integration, or connected to other devices and components formed on the same substrate for increased integration.Type: GrantFiled: July 16, 2001Date of Patent: October 11, 2005Inventors: Anisul Khan, Ajay Kumar
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Publication number: 20050211664Abstract: Embodiments of optical waveguides and method for their fabrication are provided herein. In one embodiment, a method of making an optical waveguide, includes the steps of providing a substrate comprising a semiconductor layer disposed on a first insulating layer. A hard mask is formed on the semiconductor layer. An opening is then etched in the semiconductor layer to expose a portion of the first insulating layer using the hard mask. A core material is deposited on the first insulating layer to fill the opening. The core material is then planarized and the hard mask removed. A top cladding layer is finally deposited over the core material.Type: ApplicationFiled: May 16, 2005Publication date: September 29, 2005Inventors: Anisul Khan, Ajay Kumar
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Patent number: 6827869Abstract: The present disclosure pertains to our discovery of a particularly efficient method for etching a multi-part cavity in a substrate. The method provides for first etching a shaped opening, depositing a protective layer over at least a portion of the inner surface of the shaped opening, and then etching a shaped cavity directly beneath and in continuous communication with the shaped opening. The protective layer protects the etch profile of the shaped opening during etching of the shaped cavity, so that the shaped opening and the shaped cavity can be etched to have different shapes, if desired. In particular embodiments of the method of the invention, lateral etch barrier layers and/or implanted etch stops are also used to direct the etching process. The method of the invention can be applied to any application where it is necessary or desirable to provide a shaped opening and an underlying shaped cavity having varying shapes.Type: GrantFiled: July 11, 2002Date of Patent: December 7, 2004Inventors: Dragan Podlesnik, Thorsten Lill, Jeff Chinn, Shaoher X. Pan, Anisul Khan, Maocheng Li, Yiqiong Wang
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Patent number: 6802933Abstract: This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.Type: GrantFiled: December 18, 2000Date of Patent: October 12, 2004Inventors: Anisul Khan, Ajay Kumar, Jeffrey D. Chinn, Dragan Podlesnik
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Patent number: 6696365Abstract: A method of etching high aspect ratio, anisotropic deep trench openings in a silicon substrate coated with a multilayer mask comprising in sequence a pad oxide layer, a silicon nitride layer, a doped or undoped silicon oxide hard mask layer, a polysilicon hard mask layer, an antireflection coating and a patterned photoresist layer in a single chamber comprising patterning the antireflection coating and hard mask layer, removing the photoresist and antireflection layers with oxygen, using the patterned polysilicon as a hard mask layer etching an opening in the silicon oxide hard mask layer, the silicon nitride layer and the pad oxide layer, removing the polysilicon hard mask layer with CF4/CHF3, and etching an anisotropic deep trench in the silicon substrate using the patterned silicon oxide hard mask layer as a mask and an etchant mixture including nitrogen trifluoride that self-cleans the chamber.Type: GrantFiled: January 7, 2002Date of Patent: February 24, 2004Assignee: Applied Materials, Inc.Inventors: Ajay Kumar, Anisul Khan, Sanjay Thekdi, Dragan V. Podlesnik
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Patent number: 6642127Abstract: A method and apparatus for dicing a semiconductor wafer using a plasma etch process. The method begins by applying a patterned mask to the integrated circuits on a wafer. The pattern covers the circuits and exposes the streets between the dice. Next, the method deposits a uniform layer of adhesive material upon a carrier wafer. The wafer to be diced is affixed to the carrier wafer via the adhesive material that is sandwiched between the bottom surface of the wafer to be diced and the top surface of the carrier wafer. The combination assembly of the carrier wafer, adhesive and wafer to be diced is placed in an etch reactor that is capable of etching silicon. When the reactive gas is applied to the combination assembly, the etch plasma will consume the unprotected silicon within the streets and dice the wafer into individual integrated circuit chips. The carrier wafer is then removed from the etch chamber with the dice still attached to the adhesive layer.Type: GrantFiled: October 19, 2001Date of Patent: November 4, 2003Assignee: Applied Materials, Inc.Inventors: Ajay Kumar, Padmapani C. Nallan, Anisul Khan, Dragan V. Podlesnik
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Patent number: 6642151Abstract: The present invention provides novel etching techniques for etching Si—Ge, employing SF6/fluorocarbon etch chemistries at a low bias power. These plasma conditions are highly selective to organic photoresist. The techniques of the present invention are suitable for fabricating optically smooth Si—Ge surfaces. A cavity was etched in a layer of a first Si—Ge composition using SF6/C4F8 etch chemistry at low bias power. The cavity was then filled with a second Si—Ge composition having a higher refractive index than the first Si—Ge composition. A waveguide was subsequently fabricated by depositing a cladding layer on the second Si—Ge composition that was formed in the cavity. In a further embodiment a cluster tool is employed for executing processing steps of the present invention inside the vacuum environment of the cluster tool. In an additional embodiment a manufacturing system is provided for fabricating waveguides of the present invention.Type: GrantFiled: March 6, 2002Date of Patent: November 4, 2003Assignee: Applied Materials, IncInventors: Anisul Khan, Ajay Kumar, Padmapani Nallan
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Publication number: 20030189024Abstract: Openings of variable shape are made sequentially by alternately etching an opening in silicon and depositing a conformal fluorocarbon polymer on the sidewalls. This polymer protects the sidewalls of the opening from further etching. An isotropic etch can be carried out to change the profile of the etched feature, and for lift-off of the etched feature from the silicon substrate.Type: ApplicationFiled: April 8, 2002Publication date: October 9, 2003Applicant: Applied Materials Inc.Inventors: Anisul Khan, Sharma V. Pamarthy, Sanjay Thekdi, Ajay Kumar
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Publication number: 20030176075Abstract: The present invention provides novel etching techniques for etching Si—Ge, employing SF6/fluorocarbon etch chemistries at a low bias power. These plasma conditions are highly selective to organic photoresist. The techniques of the present invention are suitable for fabricating optically smooth Si—Ge surfaces. A cavity was etched in a layer of a first Si—Ge composition using SF6/C4F8 etch chemistry at low bias power. The cavity was then filled with a second Si—Ge composition having a higher refractive index than the first Si—Ge composition. A waveguide was subsequently fabricated by depositing a cladding layer on the second Si—Ge composition that was formed in the cavity. In a further embodiment a cluster tool is employed for executing processing steps of the present invention inside the vacuum environment of the cluster tool. In an additional embodiment a manufacturing system is provided for fabricating waveguides of the present invention.Type: ApplicationFiled: March 6, 2002Publication date: September 18, 2003Applicant: Applied Materials, Inc.Inventors: Anisul Khan, Ajay Kumar, Padmapani Nallan
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Patent number: 6593244Abstract: A process for etching a pattern-masked conductor substrate anisotropically so as to obtain very high etch rates comprising adding a polymer-forming fluorocarbon gas and an etch gas at high flow rates to an etch chamber at etching pressures of 77 millitorr to 100 Torr using a high source power and bias power to the substrate support electrode to form a high density plasma. The gases can be added together, sequentially or alternately.Type: GrantFiled: September 11, 2000Date of Patent: July 15, 2003Assignee: Applied Materials Inc.Inventors: Yiqiong Wang, Anisul Khan, Ajay Kumar, Dragan Podlesnik, Sharma V. Pamarthy