Patents by Inventor Anita B. Rau

Anita B. Rau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and apparatus for digital circuit design generation
    Patent number: 6952816
    Abstract: A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for generating a circuit design from a functional specification according to at least one design objective. An intermediate representation of the functional specification is formed. The intermediate representation is analyzed for identifying a physical instantiation that will possibly result in unacceptable interconnect delay or congestion. Functional units are allocated from among a plurality of candidate functional units for performing operations of the intermediate representation. Operations are scheduled to occur at specified times on said selected functional units. An architectural representation of the circuit design is formed according to results of scheduling.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: October 4, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Shail Aditya Gupta, Anita B. Rau, Mukund Sivaraman, Darren C. Conquist, Robert S. Schreiber, Michael S. Schlansker, Bantwal Ramakrishna Rau
  • Digital circuit synthesis including timing convergence and routability
    Publication number: 20040068711
    Abstract: A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for generating a circuit design from a functional specification according to at least one design objective. An intermediate representation of the functional specification is formed. The intermediate representation is analyzed for identifying a physical instantiation that will possibly result in unacceptable interconnect delay or congestion. Functional units are allocated from among a plurality of candidate functional units for performing operations of the intermediate representation. Operations are scheduled to occur at specified times on said selected functional units. An architectural representation of the circuit design is formed according to results of scheduling.
    Type: Application
    Filed: October 7, 2002
    Publication date: April 8, 2004
    Inventors: Shail-Aditya Gupta, Bantwal Ramakrishna Rau, Anita B. Rau, Mukund Sivaraman, Darren C. Conquist, Robert S. Schreiber, Michael S. Schlansker