Abstract: A method includes associating, by a processing device, a set of dies of a block family with a die family, wherein the block family is associated with a first threshold voltage offset bin for voltage offsets to be applied in a read operation; and responsive to detecting a triggering event, associating each die of the set of dies with a second threshold voltage offset bin for voltage offsets to be applied in a read operation, wherein the second threshold voltage offset bin is selected based on a representative die of the set of dies associated with the die family.

Abstract: A method includes associating, by a processing device, a set of dies of a block family with a die family, wherein the block family is associated with a first threshold voltage offset bin for voltage offsets to be applied in a read operation; and responsive to detecting a triggering event, associating each die of the set of dies with a second threshold voltage offset bin for voltage offsets to be applied in a read operation, wherein the second threshold voltage offset bin is selected based on a representative die of the set of dies associated with the die family.

Abstract: A measure associated with a characteristic of a die of a memory device is obtained. It is determined whether the measure satisfies a first criterion to group one or more die into a first die family. If it is determined that the measure satisfies the first criterion, the die is associated with the first die family.

Abstract: A measure associated with a characteristic of a die of a memory device is obtained. It is determined whether the measure satisfies a first criterion to group one or more die into a first die family. If it is determined that the measure satisfies the first criterion, the die is associated with the first die family.

Abstract: An integrated circuit, where a hard macro is resident within the integrated circuit. The hard macro receives a clock signal at a frequency that is below the operational frequency of the integrated circuit, and produces a clock signal having a frequency that is at least equal to the operational frequency of the integrated circuit. The hard macro has a first input that receives a first signal from the tester. A second input receives a second signal from the tester, offset by substantially ninety degrees from the phase of the first signal. A speed select input receives a signal, where the signal is selectively set at one of a logical high indicating a first multiplier to be applied in the hard macro, and a logical low indicating a second multiplier to be applied in the hard macro. A clock multiplication circuit receives the first signal, selectively receives the second signal, and receives the speed select signal, and produces the clock signal.