Abstract: A sense amplifier circuit can be coupled to a match line for receiving a match line voltage and to a low potential line for receiving a low potential voltage from a memory array. The sense amplifier circuit can include a charging circuit coupled between a power supply voltage and the match line voltage that comprises no p-channel transistors. A discharging circuit can be coupled between the low potential voltage and a ground supply voltage. An n-channel sensing device can coupled to detect a potential difference between the match line voltage and the low potential voltage.

Abstract: A sense amplifier circuit with faster sensing speed and improved insensitivities to fabrication process variations (i.e., eliminated functional failures) is provided herein. According to one embodiment, the sense amplifier circuit associated with a row of memory cells within a memory device may include a charging portion, which is coupled for receiving a reference voltage that is supplied to at least one additional sense amplifier circuit within the memory device. The reference voltage is provided by a current reference generator, which is coupled to the sense amplifier circuit(s) for detecting: (i) a maximum amount of current that can pass through one compare stack within the memory cell array, or (ii) a difference between the maximum amount of current and the current contribution of an n-channel current source within the sense amplifier circuit. A memory device and method of operating one embodiment of the improved sense amplifier circuit are also provided herein.

Abstract: A content addressable memory (CAM) device (200) can equalize a potential between a match line (202) and corresponding pseudo-supply (PVSS) line (204) in a pre-sense operation. In a sense operation, a sensing device (P4) can determine a match condition exists when the match line (202) potential varies from the PVSS line (204) potential. Complementary compare data lines (CD and BCD) can be equalized with one another in a pre-sense operation, while one compare data line (CD or BCD) can be equalized with bit lines (BB1 and/or BB2) in the sensing operation.

Abstract: A sense amplifier for a content addressable memory (CAM) device can utilize charge sharing between a match line and a pseudo-supply line to indicate a mis-match indication. A sense amplifier (200) can include match line (202) that can be precharged to a high supply potential (VCC), a sense node (206), and a pseudo-VSS (PVSS) line (204) that can be precharged to a low supply potential (VSS). In a match result, match line (202) can remain precharged, keeping sense device (P2) turned off, and sense node (206) remains low, generating a low output signal (SAOUT). In a mis-match result, match line (202) and sense node (206) can be equalized. A resulting drop in match line (202) potential can turn on sense device (P2), and sense node (206) can be pulled high. As a result, output signal (SAOUT) can be driven high.

Abstract: The present invention provides an integrated parallel and serial programming interface that can be selected between either a parallel programming mode or a serial programming mode. The present invention provides a control logic circuit for selecting between the parallel and serial modes. The present invention also includes a parallel and serial detection circuit. The control logic sends a signal to an interface circuit that selects between a serial programming mode and a parallel programming mode based on the outputs of the parallel and serial detection circuits.

Abstract: An I/O interface circuit which is capable of tolerating the application of an overvoltage condition to a corresponding I/O pad but which also has a relatively low trip point voltage includes an overvoltage detection circuit configured to have a trip point at a first voltage provided by a voltage divider circuit. The voltage divider circuit may include a pair of transistors coupled in series between a voltage source having a second voltage and ground. In such cases, the first voltage may be approximately equal to the difference between the second voltage and a threshold voltage of one of the pair of transistors. Alternatively, the voltage divider circuit may include a NAND gate having an output coupled to the overvoltage detection circuit and an input coupled to receive a second voltage. The second voltage may be determined by a voltage at an I/O pad of the I/O interface and one or more diodes coupled between the I/O pad and the NAND gate.

Abstract: A programmable bus hold circuit which may find application in programmable logic devices, memories and other I/O devices may include a first element for receiving a voltage from an I/O pad and programmable circuitry coupled to the first element for controlling whether the voltage at the pad is to be held its current logic level. The first element may be a logic gate (such as a NOR gate) the programmable circuit may include a tristatable buffer (e.g., under the control of a memory cell or other programmable bit capable of enabling or disabling the programmable bus hold circuit) or a switch (e.g., a transistor).

Abstract: A sense amplifier that includes a sensing circuit, a first feedback circuit, and an output buffer. The first feedback circuit is coupled to an output of the sensing circuit and is configured in a feedback arrangement with the output buffer. The output of the sensing circuit provides an output signal having a first slew rate as the output signal transitions from a first logic state to a second logic state. The first feedback circuit may increase the slew rate of the output signal. The sense amplifier may also include a second feedback circuit coupled to the output of the sensing circuit and configured in a feedback arrangement with the output buffer. The second feedback circuit may increase a second slew rate of the output signal as the output signal transitions from the second logic state to the first logic state. The sense amplifier may be a current sense amplifier that may be used to sense the amount of current flowing through a nonvolatile memory circuit.

Abstract: A method for coding programming instructions in a complex programmable logic device (CPLD). In one embodiment, a CPLD has an instruction storage element comprising a first number of bits and requiring a first number of clock cycles to load the first number of bits. A novel method is used to instruct the device to perform at least one function comprising the steps of serially shifting a first instruction into the instruction storage element in a second number of clock cycles, and serially shifting a second instruction into the instruction storage element in a third number of clock cycles. The third number of clock cycles may be less than the first number of clock cycles. The third number of clock cycles may also be less than the second number of clock cycles. In one embodiment, the third number of clock cycles comprises one clock cycle.

Abstract: The present invention provides a circuit for supplying a verifying reference and measurement voltage for use in verifying the programming of a programmable cell. The present invention provides the verifying reference and measurement voltage through internal circuitry on the cell and eliminate any requirement for an externally provided reference voltage. The verifying voltage is provided by modifying the programming voltage. The programming voltage is stepped down or stepped up through the use of internal circuitry to provide the reference and measurement voltage.