Patents by Inventor Anitha Kalva
Anitha Kalva has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240132083Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.Type: ApplicationFiled: October 23, 2022Publication date: April 25, 2024Inventors: Anitha Kalva, Jae Wu, Shantanu Sarangi, Sailendra Chadalavada, Milind Sonawane, Chen Fang, Abilash Nerallapally
-
Patent number: 11810632Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.Type: GrantFiled: August 22, 2022Date of Patent: November 7, 2023Assignee: NVIDIA CorporationInventors: Anitha Kalva, Jue Wu
-
Patent number: 11768241Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.Type: GrantFiled: December 20, 2022Date of Patent: September 26, 2023Assignee: NVIDIA CorporationInventors: Anitha Kalva, Jue Wu
-
Publication number: 20230143807Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.Type: ApplicationFiled: December 20, 2022Publication date: May 11, 2023Inventors: Anitha Kalva, Jue Wu
-
Patent number: 11573269Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.Type: GrantFiled: July 15, 2021Date of Patent: February 7, 2023Assignee: NVIDIA CorporationInventors: Anitha Kalva, Jue Wu
-
Publication number: 20220399069Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.Type: ApplicationFiled: August 22, 2022Publication date: December 15, 2022Inventors: Anitha Kalva, Jue Wu
-
Publication number: 20220365857Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements (such as processors), a selected independent processing element is taken offline (e.g., by stopping functional operation of the independent processing element), and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation (e.g., standard application-specific operations). This enables the selected processing element to be robustly tested without stopping the regular operation of the integrated circuit.Type: ApplicationFiled: May 13, 2021Publication date: November 17, 2022Inventors: Sailendra Chadalavada, Anitha Kalva, Abilash Nerallapally, Milind Sonawane, Shantanu Sarangi, Ashok Aravamudhan, Sridharan Ramakrishnan, Sam Edirisooriya, Hari Krishnan
-
Patent number: 11424000Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.Type: GrantFiled: December 24, 2020Date of Patent: August 23, 2022Assignee: NVIDIA CORPORATIONInventors: Anitha Kalva, Jue Wu
-
Publication number: 20210341537Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.Type: ApplicationFiled: July 15, 2021Publication date: November 4, 2021Inventors: Anitha Kalva, Jue Wu
-
Patent number: 11079434Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.Type: GrantFiled: October 10, 2019Date of Patent: August 3, 2021Assignee: NVIDIA CorporationInventors: Anitha Kalva, Jue Wu
-
Publication number: 20210151118Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.Type: ApplicationFiled: December 24, 2020Publication date: May 20, 2021Inventors: Anitha Kalva, Jue Wu
-
Patent number: 10902933Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.Type: GrantFiled: August 30, 2019Date of Patent: January 26, 2021Assignee: NVIDIA CorporationInventors: Anitha Kalva, Jue Wu
-
Publication number: 20200116783Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.Type: ApplicationFiled: October 10, 2019Publication date: April 16, 2020Inventors: Anitha Kalva, Jue Wu
-
Publication number: 20200075116Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.Type: ApplicationFiled: August 30, 2019Publication date: March 5, 2020Inventors: Anitha Kalva, Jue Wu