Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.

Abstract: Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.

Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.

Abstract: An apparatus and method are provided for handling protocol conversion. The apparatus has interconnect circuitry for routing messages between components coupled to the interconnect circuitry in a manner that conforms to a first communication protocol. Protocol conversion circuitry is coupled between the interconnect circuitry and an external communication path, for converting messages between the first communication protocol and a second communication protocol that has a layered architecture comprising multiple layers. The protocol conversion circuitry has a gateway component forming one of the components coupled to the interconnect circuitry, and a controller coupled with the gateway component and used to control connection with the external communication path.

Abstract: An apparatus and method are provided for handling protocol conversion. The apparatus has interconnect circuitry for routing messages between components coupled to the interconnect circuitry in a manner that conforms to a first communication protocol. Protocol conversion circuitry is coupled between the interconnect circuitry and an external communication path, for converting messages between the first communication protocol and a second communication protocol that has a layered architecture comprising multiple layers. The protocol conversion circuitry has a gateway component forming one of the components coupled to the interconnect circuitry, and a controller coupled with the gateway component and used to control connection with the external communication path.

Abstract: A data processing apparatus is provided comprising first processing circuitry. Interrupt generating circuitry generates an outgoing interrupt in response to the first processing circuitry becoming unresponsive. Interrupt receiving circuitry receives an incoming interrupt, which indicates that second processing circuitry has become unresponsive, and in response to receiving the incoming interrupt, causes the data processing apparatus to access data managed by the second processing circuitry.

Abstract: A data processing apparatus is provided that includes monitor circuitry to produce local trace data indicating behaviour of the data processing apparatus. Interface circuitry communicates with a second data processing apparatus and encoding circuitry produces an encoded instruction to cause the local trace data to be stored in storage circuitry of the second data processing apparatus or to be output at output circuitry of the second data processing apparatus. The interface circuitry transmits the encoded instruction to the second data processing apparatus.

Abstract: An apparatus includes a first device configured to generate a transaction request targeted to a first address, a switch, coupled to the first device and configured to the route the transaction request, a port coupled to the peripheral switch and the data processing network, and a system memory management unit, coupled to the port. The system memory management unit is configured for receiving an address query for the first address from the peripheral port translating the first address to a second address, accessing attributes of a device associated with the second address and responding to the query. Access validation for the transaction request is confirmed or denied dependent upon the second address and the attributes of the device associated with the second address. The first device may be a peripheral device, the switch may be a peripheral switch and the port may be a peripheral port.

Abstract: A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

Abstract: A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

Abstract: An apparatus and method are provided for processing burst read transactions. The apparatus has a master device and a slave device coupled to the master device via a connection medium. The master device comprises processing circuitry for initiating a burst read transaction that causes the master device to issue to the slave device, via the connection medium, an address transfer specifying a read address. The slave device is arranged to process the burst read transaction by causing a plurality of data items required by the burst read transaction to be obtained based on the read address specified by the address transfer, and by performing a plurality of data transfers over the connection medium in order to transfer the plurality of data items to the master device.

Abstract: An apparatus includes processor circuitry to perform data processing operations. Interface circuitry forms a connection to a plurality of other apparatuses and receives a foreign exception message indicative of a foreign exception event having been triggered on one of the other apparatuses. In response to receiving the foreign exception message, the interface circuitry forwards the foreign exception message to a set of the plurality of other apparatuses.

Abstract: An apparatus and method are provided for processing burst read transactions. The apparatus has a master device and a slave device coupled to the master device via a connection medium. The master device comprises processing circuitry for initiating a burst read transaction that causes the master device to issue to the slave device, via the connection medium, an address transfer specifying a read address. The slave device is arranged to process the burst read transaction by causing a plurality of data items required by the burst read transaction to be obtained based on the read address specified by the address transfer, and by performing a plurality of data transfers over the connection medium in order to transfer the plurality of data items to the master device.

Abstract: An apparatus includes a first device configured to generate a transaction request targeted to a first address, a switch, coupled to the first device and configured to the route the transaction request, a port coupled to the peripheral switch and the data processing network, and a system memory management unit, coupled to the port. The system memory management unit is configured for receiving an address query for the first address from the peripheral port translating the first address to a second address, accessing attributes of a device associated with the second address and responding to the query. Access validation for the transaction request is confirmed or denied dependent upon the second address and the attributes of the device associated with the second address. The first device may be a peripheral device, the switch may be a peripheral switch and the port may be a peripheral port.

Abstract: A method for correlating first and second local time counts in first and second integrated circuits is provided. The first and second integrated circuits communicate via a communication network. A separate time control signal path is also provided between the integrated circuits. The method comprises determining a signal propagation latency associated with propagation of a latency determining signal between the integrated circuits on the time control signal path, and correlating the first and second local time counts in dependence on the signal propagation latency and a time correlating signal transmitted on the time control signal path.

Abstract: An apparatus includes processor circuitry to perform data processing operations. Interface circuitry forms a connection to a plurality of other apparatuses and receives a foreign exception message indicative of a foreign exception event having been triggered on one of the other apparatuses. In response to receiving the foreign exception message, the interface circuitry forwards the foreign exception message to a set of the plurality of other apparatuses.

Abstract: A data processing apparatus is provided that includes monitor circuitry to produce local trace data indicating behaviour of the data processing apparatus. Interface circuitry communicates with a second data processing apparatus and encoding circuitry produces an encoded instruction to cause the local trace data to be stored in storage circuitry of the second data processing apparatus or to be output at output circuitry of the second data processing apparatus. The interface circuitry transmits the encoded instruction to the second data processing apparatus.

Abstract: A method for correlating first and second local time counts in first and second integrated circuits is provided. The first and second integrated circuits communicate via a communication network. A separate time control signal path is also provided between the integrated circuits. The method comprises determining a signal propagation latency associated with propagation of a latency determining signal between the integrated circuits on the time control signal path, and correlating the first and second local time counts in dependence on the signal propagation latency and a time correlating signal transmitted on the time control signal path.

Abstract: A data processing apparatus is provided comprising first processing circuitry. Interrupt generating circuitry generates an outgoing interrupt in response to the first processing circuitry becoming unresponsive. Interrupt receiving circuitry receives an incoming interrupt, which indicates that second processing circuitry has become unresponsive, and in response to receiving the incoming interrupt, causes the data processing apparatus to access data managed by the second processing circuitry.

Abstract: In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic unit. The cryptographic processor also includes a nonvolatile memory to store one or more microcode instructions, wherein at least one of the one or more microcode instructions is related to a sensitive operation. The cryptographic processor also includes a controller to control execution of the one or more microcode instructions by the at least one cryptographic unit, wherein the controller is to preclude execution of the sensitive operation if the apparatus is within an untrusted state.