Patents by Inventor Anja Gissibl

Anja Gissibl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160064273
    Abstract: A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.
    Type: Application
    Filed: November 9, 2015
    Publication date: March 3, 2016
    Inventors: Matthias Stecher, Markus Menath, Andreas Zankl, Anja Gissibl
  • Patent number: 9093385
    Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: July 28, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Anja Gissibl, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
  • Patent number: 8932476
    Abstract: Apparatuses and methods are provided where porous metal is deposited on a substrate, a mask is provided on the porous metal and then an etching is performed.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 13, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kunstmann, Stefan Willkofer, Anja Gissibl, Johann Strasser, Matthias Mueller, Eva-Maria Hess
  • Publication number: 20140357055
    Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Applicant: Infineon Technologies AG
    Inventors: Anja Gissibl, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
  • Publication number: 20140217062
    Abstract: Apparatuses and methods are provided where porous metal is deposited on a substrate, a mask is provided on the porous metal and then an etching is performed.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 7, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Kunstmann, Stefan Willkofer, Anja Gissibl, Johann Strasser, Matthias Mueller, Eva-Maria Hess
  • Publication number: 20130280879
    Abstract: A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Matthias Stecher, Markus Menath, Andreas Zankl, Anja Gissibl