Patents by Inventor Anja Morgenschweis

Anja Morgenschweis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050118336
    Abstract: A process is described for depositing silicon nitride, in which the temperature in a furnace is set to from 600° C. to 645° C. The silicon nitride formed in this way is permeable to small molecules, such as in particular hydrogen molecules, yet nevertheless retains its etching selectivity with respect to silicon dioxide.
    Type: Application
    Filed: August 27, 2002
    Publication date: June 2, 2005
    Inventors: Henry Bernhardt, Michael Stadtmueller, Dietmar Ottenwaelder, Anja Morgenschweis
  • Patent number: 6734077
    Abstract: A method for fabricating a trench capacitor for a semiconductor memory includes forming a masking layer in a trench that is disposed in a substrate. Nanocrystallites, which are used to pattern the masking layer, are deposited on the masking layer. Microtrenches are etched into the substrate in a lower region of the trench by the patterned masking layer. The microtrenches form a roughened trench sidewall. As a result, the outer capacitor electrode is formed with a larger surface area, allowing the trench capacitor to have a higher capacitance.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: May 11, 2004
    Assignee: Infineon Technologies AG
    Inventors: Matthias Förster, Kristin Schupke, Anja Morgenschweis, Anett Moll, Jens-Uwe Sachse
  • Patent number: 6645839
    Abstract: A method for improving a doping profile using gas phase doping is described. In the method, silicon nitride and/or products of decomposition from a silicon nitride deposition are introduced in a process chamber before or during the actual gas phase doping. This allows the doping profile to be significantly improved.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: November 11, 2003
    Assignee: Infineon Technologies AG
    Inventors: Moritz Haupt, Anja Morgenschweis, Dietmar Ottenwälder, Uwe Schröder
  • Publication number: 20030068867
    Abstract: A method for fabricating a trench capacitor for a semiconductor memory includes forming a masking layer in a trench that is disposed in a substrate. Nanocrystallites, which are used to pattern the masking layer, are deposited on the masking layer. Microtrenches are etched into the substrate in a lower region of the trench by the patterned masking layer. The microtrenches form a roughened trench sidewall. As a result, the outer capacitor electrode is formed with a larger surface area, allowing the trench capacitor to have a higher capacitance.
    Type: Application
    Filed: September 4, 2002
    Publication date: April 10, 2003
    Inventors: Matthias Forster, Kristin Schupke, Anja Morgenschweis, Anett Moll, Jens-Uwe Sachse
  • Publication number: 20030013283
    Abstract: A method for improving a doping profile using gas phase doping is described. In the method, silicon nitride and/or products of decomposition from a silicon nitride deposition are introduced in a process chamber before or during the actual gas phase doping. This allows the doping profile to be significantly improved.
    Type: Application
    Filed: May 6, 2002
    Publication date: January 16, 2003
    Inventors: Moritz Haupt, Anja Morgenschweis, Dietmar Ottenwalder, Uwe Schroder
  • Patent number: 6455369
    Abstract: A method for fabricating a trench capacitor, that includes steps of: providing a silicon substrate; forming a trench, having a lower region and a surface, in the silicon substrate; and forming a doped layer in the silicon substrate in the lower region of the trench. In addition, a roughened silicon layer that has silicon grains with a diameter ranging from essentially 10 to 100 nm is produced in the lower region of the trench. A dielectric intermediate layer is applied on the roughened silicon layer, and the trench is filled with a doped layer.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: September 24, 2002
    Assignee: Infineon Technologies AG
    Inventors: Matthias Förster, Jörn Lützen, Martin Gutsche, Anja Morgenschweis
  • Publication number: 20020081801
    Abstract: A microroughness on a surface is produced in a single process step by forming semiconductor grains directly from a process gas. The semiconductor grains are finely distributed on the surface. As a result of forming the microroughness in a single process step, time and costs are saved during fabrication.
    Type: Application
    Filed: July 9, 2001
    Publication date: June 27, 2002
    Inventors: Matthias Forster, Anja Morgenschweis, Torsten Martini, Jens-Uwe Sachse
  • Publication number: 20020072171
    Abstract: A method for fabricating a trench capacitor, that includes steps of: providing a silicon substrate; forming a trench, having a lower region and a surface, in the silicon substrate; and forming a doped layer in the silicon substrate in the lower region of the trench. In addition, a roughened silicon layer that has silicon grains with a diameter ranging from essentially 10 to 100 nm is produced in the lower region of the trench. A dielectric intermediate layer is applied on the roughened silicon layer, and the trench is filled with a doped layer.
    Type: Application
    Filed: August 20, 2001
    Publication date: June 13, 2002
    Inventors: Matthias Forster, Jorn Lutzen, Martin Gutsche, Anja Morgenschweis