Patents by Inventor ANJALI SINGHAI JAIN
ANJALI SINGHAI JAIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240334245Abstract: Examples described herein relate to a network interface device that performs: offloading processing of fragments of a packet to an accelerator; processing non-fragmented packets; and prioritizing dropping of fragments of the packet over dropping of non-fragmented packets. Offloading processing of fragments of the packet to the accelerator can include: the accelerator performing: reassembling the fragments of the packet into a first reassembly packet; and based on congestion associated with at least one of the fragments of the packet of the first reassembly packet: dropping fragments of the first reassembly packet associated with one or more flows; halting reassembly of the first reassembly packet; and forwarding a second packet to a host system, wherein the second packet indicates that congestion occurred, identifies one or more impacted flows, and indicates a number of dropped packet fragments.Type: ApplicationFiled: June 7, 2024Publication date: October 3, 2024Inventors: John J. BROWNE, Andrey CHILIKIN, Elazar COHEN, Joseph HASTING, James CLEE, Jerry PIROG, Jamison D. WHITESELL, Ambalavanar ARULAMBALAM, Anjali Singhai JAIN, Andrew CUNNINGHAM, Ruben DAHAN
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Publication number: 20240283756Abstract: Examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (ACKs), into one or more kernel space queues that are also accessible in user space.Type: ApplicationFiled: January 29, 2024Publication date: August 22, 2024Inventors: Shaopeng HE, Cunming LIANG, Jiang YU, Ziye YANG, Ping YU, Bo CUI, Jingjing WU, Liang MA, Hongjun NI, Zhiguo WEN, Changpeng LIU, Anjali Singhai JAIN, Daniel DALY, Yadong LI
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Patent number: 12026110Abstract: Examples described herein relate to a device indicating a number of available interrupt messages that is more than physical resources available to store the available interrupt messages and allocating one or more physical resources to provide one or more interrupt messages based on allocation of the one or more interrupt messages to a destination entity. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level and allocate the requested maximum permitted allocation of interrupt messages for use in a configuration region of a device. However, based on unavailability of a physical resource to store a first interrupt message, allocation of the first interrupt message to a destination entity may not be permitted.Type: GrantFiled: March 10, 2020Date of Patent: July 2, 2024Assignee: Intel CorporationInventors: Linden Cornett, Eliel Louzoun, Anjali Singhai Jain, Ronen Aharon Hyatt, Danny Volkind, Noam Elati, Nadav Turbovich
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Patent number: 11989573Abstract: Techniques for providing adaptive virtual function (VF) drivers capable of operating with physical devices having a plurality of different hardware configurations are described. In one embodiment, for example, an apparatus may include logic to implement a virtual machine (VM), the logic to initialize an adaptive virtual function (VF) driver to facilitate communication between the VM and a physical device to be virtualized, establish communication between the adaptive VF driver and a physical function (PF) driver of the hypervisor for the physical device, activate a standard feature set for the adaptive VF driver to execute on a PF of the physical device, and negotiate activation of an advanced feature set for the adaptive VF driver to execute on the PF, the adaptive VF driver to provide the advanced feature set to the PF, the PF activate each feature of the advanced feature set supported by the PF.Type: GrantFiled: June 1, 2023Date of Patent: May 21, 2024Assignee: INTEL CORPORATIONInventors: Anjali Singhai Jain, Mitu Aggarwal, Parthasarathy Sarangam, Donald Wood, Jesse Brandeburg, Mitchell A. Williams
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Patent number: 11936571Abstract: Examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (ACKs), into one or more kernel space queues that are also accessible in user space.Type: GrantFiled: November 4, 2022Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Shaopeng He, Cunming Liang, Jiang Yu, Ziye Yang, Ping Yu, Bo Cui, Jingjing Wu, Liang Ma, Hongjun Ni, Zhiguo Wen, Changpeng Liu, Anjali Singhai Jain, Daniel Daly, Yadong Li
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Publication number: 20240036895Abstract: Techniques for providing adaptive virtual function (VF) drivers capable of operating with physical devices having a plurality of different hardware configurations are described. In one embodiment, for example, an apparatus may include logic to implement a virtual machine (VM), the logic to initialize an adaptive virtual function (VF) driver to facilitate communication between the VM and a physical device to be virtualized, establish communication between the adaptive VF driver and a physical function (PF) driver of the hypervisor for the physical device, activate a standard feature set for the adaptive VF driver to execute on a PF of the physical device, and negotiate activation of an advanced feature set for the adaptive VF driver to execute on the PF, the adaptive VF driver to provide the advanced feature set to the PF, the PF activate each feature of the advanced feature set supported by the PF.Type: ApplicationFiled: June 1, 2023Publication date: February 1, 2024Applicant: INTEL CORPORATIONInventors: ANJALI SINGHAI JAIN, MITU AGGARWAL, PARTHASARATHY SARANGAM, DONALD WOOD, JESSE BRANDEBURG, MITCHELL A. WILLIAMS
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Publication number: 20240028381Abstract: A network interface device executes an input/output (I/O) virtualization manager to identify a virtual device defined to include resources of a particular virtual functions in a plurality of virtual functions associated with a physical function of a device. An operation is identified to be performed between the virtual device and a system image hosted by a host system coupled to the network interface device. The network interface device emulates the virtual device in the operation using the I/O virtualization manager.Type: ApplicationFiled: September 28, 2023Publication date: January 25, 2024Applicant: Intel CorporationInventors: Shaopeng He, Yadong Li, Anjali Singhai Jain, Eliel Louzoun, Israel Ben-Shahar, Brad A. Burres, Bartosz Pawlowski, Anton Nadezhdin, Rashmi Hanagal Nagabhushana, Rupin H. Vakharwala
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Publication number: 20240031289Abstract: Examples described herein relate to a network interface device. The network interface device can include circuitry that is to: perform a route lookup for a packet based on first and second lookup operations, wherein the first lookup operation comprises a longest prefix match (LPM) to output a route identifier based on a destination Internet Protocol (IP) address of the packet and wherein the second look up operation comprises an exact match operation to determine an action based on the route identifier and a packet header.Type: ApplicationFiled: September 30, 2023Publication date: January 25, 2024Inventors: Arunkumar BALAKRISHNAN, Anurag AGRAWAL, Elazar COHEN, Anjali Singhai JAIN
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Patent number: 11831742Abstract: Methods, apparatus, and systems for implementing a semi-flexible Receive Segment Coalescing (RSC) control path. Logic for evaluating packet coalescing open flow criteria and close flow criteria are implemented in hardware on a network device that receives packets from one or more networks. packet coalescing open profiles and packet coalescing close profiles are also stored on the network device, wherein each packet coalescing open profile defines a set of packet coalescing open flow criteria to be applied for that packet coalescing open profile and each packet coalescing close profile defines a set of packet coalescing close flow criteria to be applied for that packet coalescing open profile. packet coalescing open flow and close flow profiles are then assigned to packet coalescing-enabled receive queues on the network device and corresponding open and flow criteria are used to perform packet coalescing-related processing of packets in the receive queues.Type: GrantFiled: December 12, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Linden Cornett, Anjali Singhai Jain, Noam Elati
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Publication number: 20230362284Abstract: Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file.Type: ApplicationFiled: June 23, 2023Publication date: November 9, 2023Inventors: Peter P. WASKIEWICZ, JR., Anjali Singhai JAIN, Neerav PARIKH, Parthasarathy SARANGAM
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Patent number: 11805081Abstract: Packets received non-contiguously from a network are processed by a network interface controller by coalescing received packet payload into receive buffers on a receive buffer queue and writing descriptors associated with the receive buffers for a same flow consecutively in a receive completion queue. System performance is optimized by reusing a small working set of provisioned receive buffers to minimize the memory footprint of memory allocated to store packet data. The remainder of the provisioned buffers are in an overflow queue and can be assigned to the network interface controller if the small working set of receive buffers is not sufficient to keep up with the received packet rate. The receive buffer queue can be refilled based on either timers or when the number of buffers in the receive buffer queue is below a configurable low watermark.Type: GrantFiled: March 2, 2020Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Linden Cornett, Noam Elati, Anjali Singhai Jain, Parthasarathy Sarangam, Eliel Louzoun, Manasi Deval
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Patent number: 11743367Abstract: Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file.Type: GrantFiled: May 10, 2022Date of Patent: August 29, 2023Assignee: Intel CorporationInventors: Peter P. Waskiewicz, Jr., Anjali Singhai Jain, Neerav Parikh, Parthasarathy Sarangam
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Publication number: 20230259352Abstract: Examples described herein relate to a network interface device. In some examples, the network interface device includes a network interface device that includes a network interface, a host interface, and multiple processors. In some examples, a first processor of the multiple processors is to execute a first control plane process and an embedded software update is to occur by: installation and execution of a second control plane process on the first processor and a third control plane process is to cause utilization of the second control plane process.Type: ApplicationFiled: April 17, 2023Publication date: August 17, 2023Inventors: Kirill KAZATSKER, Keren GUY, Anjali Singhai JAIN, Matthew VICK, Jayaprakash SHANMUGAM
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Patent number: 11698804Abstract: Techniques for providing adaptive virtual function (VF) drivers capable of operating with physical devices having a plurality of different hardware configurations are described. In one embodiment, for example, an apparatus may include logic to implement a virtual machine (VM), the logic to initialize an adaptive virtual function (VF) driver to facilitate communication between the VM and a physical device to be virtualized, establish communication between the adaptive VF driver and a physical function (PF) driver of the hypervisor for the physical device, activate a standard feature set for the adaptive VF driver to execute on a PF of the physical device, and negotiate activation of an advanced feature set for the adaptive VF driver to execute on the PF, the adaptive VF driver to provide the advanced feature set to the PF, the PF activate each feature of the advanced feature set supported by the PF.Type: GrantFiled: January 27, 2021Date of Patent: July 11, 2023Assignee: INTEL CORPORATIONInventors: Anjali Singhai Jain, Mitu Aggarwal, Parthasarathy Sarangam, Donald Wood, Jesse Brandeburg, Mitchell A. Williams
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Publication number: 20230205563Abstract: Systems, methods, and devices for efficient I/O page fault handling are provided. A system may include a peripheral device that accesses guest memory of a virtual machine using direct memory access (DMA) and a processing device that that runs the virtual machine. The processing device may include a buffer allocated to receive a payload from the peripheral device while an input/output page fault corresponding to a page of the guest memory is resolved. The processing device may also include an input/output page fault queue to store a descriptor corresponding to the input/output page fault and a fault buffer queue to store a descriptor corresponding to a location of the buffer allocated to receive the payload while the input/output page fault is resolved.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Ashok Raj, Rajesh Sankaran, Anjali Singhai Jain, Patrick Maloney
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Publication number: 20230153143Abstract: Creating hybrid virtual devices using a plurality of physical functions. A processor of a device may identify a plurality of physical functions accessible to the device, the plurality of physical functions including a first physical function and a second physical function. The processor may create a virtual device to comprise the first physical function to provide a first capability and the second physical function to provide a second capability, wherein the first capability and second capability are different capabilities.Type: ApplicationFiled: January 17, 2023Publication date: May 18, 2023Applicant: Intel CorporationInventors: SHAOPENG HE, ANJALI SINGHAI JAIN, UTKARSH Y. KAKAIYA, YADONG LI, ELIEL LOUZOUN, KUN TIAN, BRADLEY BURRES, RORY HARRIS, YAN ZHAO
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Publication number: 20230109396Abstract: Examples described herein relate to a network interface device. In some examples, packet processing circuitry in the network interface device is to receive a first packet and based on the first packet being associated with an identifier for which an entry is not present in a look-up table accessible to the packet processing circuitry, the packet processing circuitry is to provide the identifier for the first packet and an action for the identifier of the first packet and cause the first packet to configure a second look-up-table accessible to the packet processing circuitry with the action for the identifier.Type: ApplicationFiled: October 1, 2022Publication date: April 6, 2023Inventors: Anjali Singhai JAIN, Nupur JAIN, Elazar COHEN, John Andrew FINGERHUT, Neha SINGH, Vinoth Kumar CHANDRA MOHAN, Alana SWEAT, Arunkumar BALAKRISHNAN
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Publication number: 20230108461Abstract: Examples described herein relate to circuitry configured to generate at least one virtual device interface to utilize the processor circuitry and provide the at least one virtual device interface to a server to assign to a process to provide the process with capability to utilize the processor circuitry. In some examples, the processor circuitry is to perform one or more of local area network access, cryptographic processing, and/or storage access. In some examples, the storage access comprises access to one or more Non-volatile Memory Express (NVMe) devices.Type: ApplicationFiled: November 30, 2022Publication date: April 6, 2023Inventors: Shaopeng HE, Anjali Singhai JAIN, Yadong LI, Eliel LOUZOUN, Bradley A. BURRES, Utkarsh Y. KAKAIYA, Kun TIAN, Baolu LU, Yan ZHAO, Madhusudan CHITTIM MUNIRATHNAM, Lingyu LIU
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Publication number: 20230053744Abstract: Examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (ACKs), into one or more kernel space queues that are also accessible in user space.Type: ApplicationFiled: November 4, 2022Publication date: February 23, 2023Inventors: Shaopeng HE, Cunming LIANG, Jiang YU, Ziye YANG, Ping YU, Bo CUI, Jingjing WU, Liang MA, Hongjun NI, Zhiguo WEN, Changpeng LIU, Anjali Singhai JAIN, Daniel DALY, Yadong LI
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Patent number: 11575620Abstract: Examples described herein relate to an apparatus including at least one memory and at least one processor communicatively coupled to the at least one memory, the at least one processor to: allocate a scheduler to an egress port and based on unavailability of an egress port, allocate the scheduler to a second egress port to cause any packet allocated to a transmit queue associated with the scheduler to be transmitted using the second egress port. In some examples, a system receives a packet at a port on a network interface, associates a port group with the packet, determines a receive queue for the packet, and copies the packet to the determined receive queue. The port group can be adjusted to remove the port or to add a second port.Type: GrantFiled: March 27, 2020Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Eliel Louzoun, Anjali Singhai Jain, Ben-Zion Friedman