Abstract: In a system-on-chip (SoC), a method is provided for partitioning access to resources. A plurality of processors is provided, including a configuration master (CM) processor, a memory, a plurality of OSs, and accessible resources. The method creates a mapping table with a plurality of entries, each entry cross-referencing a range of destination addresses with a domain ID, where each domain ID is associated with a corresponding processor. Access requests to the resource are accepted from the plurality of processors. Each access request includes a domain ID and a destination address. A mapping table is consulted to determine the range of destination addresses associated with the access request domain IDs. The accesses are authorized in response to the access request destination addresses matching the range of destination addresses in the mapping table, and the authorized access requests are sent to the destination addresses of the requested resources.

Abstract: A multistage latch-based isolation cell is provided. The isolation cell includes a latch to receive a first binary signal and an enable signal. The latch initially supplies a second binary signal with an unknown value in response to the enable port receiving an enable signal having a first polarity value, and subsequent to receiving the first binary signal with a first value, supplying the second binary signal with the first value. The isolation cell includes a delay device to receive the enable signal and to supply a delayed enable signal. A reset latch receives the second binary signal, the delayed enable signal, and a reset pulse. The reset latch supplies a third binary signal equal to the first value in response to the reset latch receiving the reset pulse, followed by the delayed enable signal with the first polarity value, followed by the second binary signal.