Abstract: A memory cell having integrated read and write assist functionality includes a storage element and first and second switching circuits. The first switching circuit is configured to selectively couple a first internal storage node of the storage element with a first bit line. The second switching circuit is configured to selectively couple a second internal storage node of the storage element with a second bit line. During a read operation, at least one of the first and second switching circuits is configured to increase a switching threshold of at least one inverter in the storage element. During a write operation, at least one of the first and second switching circuits is configured such that ground bounce associated with at least one of the first and second switching circuits assists in writing a logical state of the memory cell.

Abstract: A memory cell having integrated read and write assist functionality includes a storage element and first and second switching circuits. The first switching circuit is configured to selectively couple a first internal storage node of the storage element with a first bit line. The second switching circuit is configured to selectively couple a second internal storage node of the storage element with a second bit line. During a read operation, at least one of the first and second switching circuits is configured to increase a switching threshold of at least one inverter in the storage element. During a write operation, at least one of the first and second switching circuits is configured such that ground bounce associated with at least one of the first and second switching circuits assists in writing a logical state of the memory cell.

Abstract: A memory cell includes a storage element including a pair of cross-coupled inverters, and first switching circuitry for selectively connecting at least one internal storage node of the storage element with a corresponding bit line as a function of a first control signal. Write assist circuitry is connected between a supply node of a device of at least one of the cross-coupled inverters and a voltage supply of the memory cell, and second switching circuitry selectively couples the supply node of the device of at least one of the cross-coupled inverters with the corresponding bit line as a function of a second control signal. During a write operation, the write assist circuitry disconnects the storage element from the voltage supply, and the second circuitry connects the supply node of the device of at least one of the cross-coupled inverters with the corresponding bit line.

Abstract: Features automatically extracted from semi-structured web pages are utilized by a search engine to rank documents that include semi-structured web pages. These features include, but are not limited to, a number of reviews, a number of positive reviews, and/or a number of negative reviews from a web page that includes user reviews. These features also include a number of views of a video that is viewable by way of a semi-structured web page. The features also include a number of subscribers to broadcasts of an individual from a social networking web page and a number of contacts of an individual listed on a social networking web page.

Abstract: Features automatically extracted from semi-structured web pages are utilized by a search engine to rank documents that include semi-structured web pages. These features include, but are not limited to, a number of reviews, a number of positive reviews, and/or a number of negative reviews from a web page that includes user reviews. These features also include a number of views of a video that is viewable by way of a semi-structured web page. The features also include a number of subscribers to broadcasts of an individual from a social networking web page and a number of contacts of an individual listed on a social networking web page.