Patents by Inventor Anju Narendra

Anju Narendra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080189245
    Abstract: Data extraction for semiconductor process analysis may be implemented across multiple databases. A user may select a given level of interest, such as a wafer, a lot, or a die, and may extract specified information across more than one database if desired. The databases may include separate information such as process control information, electrical, and sort test information. Instead of coalescing the databases into one extremely unmanageable database, data can be extracted horizontally across those databases using structured queries.
    Type: Application
    Filed: September 29, 2006
    Publication date: August 7, 2008
    Inventors: Joel Fenner, Sutirtha Bhattacharya, Anju Narendra
  • Patent number: 7366575
    Abstract: Methods of controlling polishing of wafers are disclosed. In one aspect, a method may include measuring one or more pre-polish thicknesses of one or more layers of a wafer. The one or more layers may then be polished. Then a post-polish thickness of a layer of the wafer may be measured. Polishing may be controlled by using feed-forward control with the one or more pre-polish thicknesses and by using feed-back control with the post-polish thickness. Machine-accessible software to perform such methods are also disclosed as are systems in which such methods may be implemented.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: April 29, 2008
    Assignee: Intel Corporation
    Inventors: Matthew A. Ring, Scot Goerutiz, Kimberly A. Ryglelski, Anju Narendra, Kevin E. Heldrich, Brook D. Ferney
  • Publication number: 20070155284
    Abstract: Methods of controlling polishing of wafers are disclosed. In one aspect, a method may include measuring one or more pre-polish thicknesses of one or more layers of a wafer. The one or more layers may then be polished. Then a post-polish thickness of a layer of the wafer may be measured. Polishing may be controlled by using feed-forward control with the one or more pre-polish thicknesses and by using feed-back control with the post-polish thickness. Machine-accessible software to perform such methods are also disclosed as are systems in which such methods may be implemented.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Inventors: Matthew Ring, Scot Goerutiz, Kimberly Ryglelski, Anju Narendra, Kevin Heldrich, Brook Ferney
  • Patent number: 6526358
    Abstract: A fault detection and isolation system for detecting leaks and blockages in a fluid handling system having at least one component through which fluid flows includes sensors for measuring fluid conditions upstream and downstream of the component. The sensors generate signals that are representative of the upstream and downstream fluid conditions and are fed to a control algorithm. The control algorithm uses the measured fluid conditions to generate estimates of an inlet state for the component and an outlet state for the component. The control algorithm also calculates innovation sequences for the estimated inlet and outlet states, and then compares the innovation sequences to predetermined thresholds to detect leaks and blockages.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: February 25, 2003
    Assignee: General Electric Company
    Inventors: Harry Kirk Mathews, Jr., Anju Narendra, Ravi Rajamani, Bruce G. Norman, John Harry Down, Sal A. Leone, Jonathan Carl Thatcher