Patents by Inventor Anjul Patney

Anjul Patney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9747718
    Abstract: A system, method, and computer program product are provided for performing object-space shading. A primitive defined by vertices in three-dimensional (3D) space that is specific to an object defined by at least the primitive is received and a shading sample rate is computed for the primitive based on a screen-space derivative of coordinates of a pixel fragment transformed into the 3D space. A shader program is executed by a processing pipeline to compute shaded attributes for the primitive according to the computed shading sample rate.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: August 29, 2017
    Assignee: NVIDIA Corporation
    Inventors: Anjul Patney, Eric B. Enderton, Eric B. Lum, Marco Salvi, Christopher Ryan Wyman, Yubo Zhang, Yong He, G. Evan Hart, Jr., Kayvon Fatahalian, Yury Uralsky, Henry Packard Moreton, Aaron Eliot Lefohn
  • Publication number: 20160203635
    Abstract: A method, computer readable medium, and system are disclosed for rendering shadows. A frustum projected from a grid cell corresponding to a light source in light-space is defined and a graphics primitive is determined to intersect the frustum. A light-space visibility buffer is accessed to obtain a set of pixel fragment footprints corresponding to the frustum and it is identified whether each pixel fragment footprint of the pixel fragment footprints is shadowed by the graphics primitive.
    Type: Application
    Filed: January 6, 2016
    Publication date: July 14, 2016
    Inventors: Christopher Ryan Wyman, Aaron Eliot Lefohn, Anjul Patney
  • Publication number: 20160049000
    Abstract: A system, method, and computer program product are provided for performing object-space shading. A primitive defined by vertices in three-dimensional (3D) space that is specific to an object defined by at least the primitive is received and a shading sample rate is computed for the primitive based on a screen-space derivative of coordinates of a pixel fragment transformed into the 3D space. A shader program is executed by a processing pipeline to compute shaded attributes for the primitive according to the computed shading sample rate.
    Type: Application
    Filed: March 11, 2015
    Publication date: February 18, 2016
    Inventors: Anjul Patney, Eric B. Enderton, Eric B. Lum, Marco Salvi, Christopher Ryan Wyman, Yubo Zhang, Yong He, G. Evan Hart, JR., Kayvon Fatahalian, Yury Uralsky, Henry Packard Moreton, Aaron Eliot Lefohn
  • Publication number: 20160048999
    Abstract: A system, method, and computer program product are provided fir shading using a dynamic object-space grid. An object defined by triangle primitives in a three-dimensional (3D) space that is specific to the object is received and an object-space shading grid is defined for a first triangle primitive of the triangle primitives based on coordinates of the first triangle primitive in the 3D space. A shader program is executed by a processing pipeline to compute a shaded value at a point on the object-space shading grid for the first triangle primitive.
    Type: Application
    Filed: March 11, 2015
    Publication date: February 18, 2016
    Inventors: Anjul Patney, Eric B. Enderton, Eric B. Lum, Marco Salvi, Christopher Ryan Wyman, Yubo Zhang, Yong He, G. Evan Hart, JR., Kayvon Fatahalian, Yury Uralsky, Henry Packard Moreton, Aaron Eliot Lefohn
  • Publication number: 20150179142
    Abstract: A system, method, and computer program product are provided for calculating shader program intermediate values. The method includes the steps of receiving a graphics primitive for processing according to a shader program including a first set of instructions and a second set of instructions, executing the first set of instructions by a processing pipeline to calculate multi-pixel intermediate values, executing the second set of instructions by the processing pipeline to calculate per-pixel values based on at least the multi-pixel intermediate values, and repeating the receiving and executing of the first and second sets of instructions for one or more additional graphics primitives.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Applicant: NVIDIA Corporation
    Inventors: Jaakko T. Lehtinen, Samuli Matias Laine, Kayvon Fatahalian, Yong He, Anjul Patney
  • Patent number: 8860742
    Abstract: A technique for caching coverage information for edges that are shared between adjacent graphics primitives may reduce the number of times a shared edge is rasterized. Consequently, power consumed during rasterization may be reduced. During rasterization of a first graphics primitive coverage information is generated that (1) indicates cells within a sampling grid that are entirely outside an edge of the first graphics primitive and (2) indicates cells within the sampling grid that are intersected by the edge and are only partially covered by the first graphics primitive. The coverage information for the edge is stored in a cache. When a second graphics primitive is rasterized that shares the edge with the first graphics primitive, the coverage information is read from the cache instead of being recomputed.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: October 14, 2014
    Assignee: NVIDIA Corporation
    Inventors: Michael C. Shebanow, Anjul Patney
  • Patent number: 8832671
    Abstract: One embodiment of the present invention sets forth a technique for using a multi-bank register file that reduces the size of or eliminates a switch and/or staging registers that are used to gather input operands for instructions. Each function unit input may be directly connected to one bank of the multi-bank register file with neither a switch nor a staging register. A compiler or register allocation unit ensures that the register file accesses for each instruction are conflict-free (no instruction can access the same bank more than once in the same cycle). The compiler or register allocation unit may also ensure that the register file accesses for each instruction are also aligned (each input of a function unit can only come from the bank connected to that input).
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: September 9, 2014
    Assignee: NVIDIA Corporation
    Inventors: Anjul Patney, William J. Dally
  • Patent number: 8555035
    Abstract: One embodiment of the present invention sets forth a technique for using a multi-bank register file that reduces the size of or eliminates a switch and/or staging registers that are used to gather input operands for instructions. Each function unit input may be directly connected to one bank of the multi-bank register file with neither a switch nor a staging register. A compiler or register allocation unit ensures that the register file accesses for each instruction are conflict-free (no instruction can access the same bank more than once in the same cycle). The compiler or register allocation unit may also ensure that the register file accesses for each instruction are also aligned (each input of a function unit can only come from the bank connected to that input).
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: October 8, 2013
    Assignee: NVIDIA Corporation
    Inventors: Anjul Patney, William J. Dally
  • Publication number: 20120280992
    Abstract: The grid walk sampling technique is an efficient sampling algorithm aimed at optimizing the cost of triangle rasterization for modern graphics workloads. Grid walk sampling is an iterative rasterization algorithm that intelligently tests the intersection of triangle edges with multi-cell grids, determining coverage for a grid cell while identifying other cells in the grid that are either fully covered or fully uncovered by the triangle. Grid walk sampling rasterizes triangles using fewer computations and simpler computations compared with conventional highly parallel rasterizers. Therefore, a rasterizer employing grid walk sampling may compute sample coverage of triangles more efficiently in terms of power and circuitry die area compared with conventional highly parallel rasterizers.
    Type: Application
    Filed: May 1, 2012
    Publication date: November 8, 2012
    Inventors: Michael C. Shebanow, Anjul Patney
  • Publication number: 20120281004
    Abstract: A technique for caching coverage information for edges that are shared between adjacent graphics primitives may reduce the number of times a shared edge is rasterized. Consequently, power consumed during rasterization may be reduced. During rasterization of a first graphics primitive coverage information is generated that (1) indicates cells within a sampling grid that are entirely outside an edge of the first graphics primitive and (2) indicates cells within the sampling grid that are intersected by the edge and are only partially covered by the first graphics primitive. The coverage information for the edge is stored in a cache. When a second graphics primitive is rasterized that shares the edge with the first graphics primitive, the coverage information is read from the cache instead of being recomputed.
    Type: Application
    Filed: May 2, 2012
    Publication date: November 8, 2012
    Inventors: Michael C. Shebanow, Anjul Patney