Abstract: A method for debugging test procedures for automated device testing is disclosed. The method comprises receiving a command to update at least one modified test procedure modified during a first debugging session and saving state information for a test plan, wherein the state information comprises information regarding a breakpoint entry location, and wherein the modified test procedure is invoked within the test plan. The method subsequently comprises suspending execution of the test plan and unloading the modified test procedure. It also comprises compiling the modified test procedure to produce a compiled file and then reloading the test procedure into the test plan using the compiled file. Finally, it comprises resuming execution of the modified test procedure in a second debugging session and breaking the execution during the second debugging session at a breakpoint corresponding to the breakpoint entry location.

Abstract: A method for performing tests using automated test equipment (ATE) is presented. The method comprises obtaining information concerning a test class using a graphical user interface. Further, it comprises generating a first header file automatically, wherein the first header file comprises the information concerning the test class. Next, it comprises importing the first header file into a test plan operable to execute using a tester operating system wherein the test plan comprises instances of the test class. It further comprises, generating a second header file from the first header file automatically, wherein the second header file is a header file for the test class. The method also comprises validating the test plan using the tester operating system. Finally, the method comprises loading the test plan and a compiled module onto the tester operating system for execution, wherein the compiled module is a compiled translation of the test class.

Abstract: A method for using shared pins in a concurrent test execution environment is disclosed. The method relates to scheduling tests in concurrently executing test flows for automated test equipment (ATE) in a way so that resources can be shared between the test flows. The method comprises determining if any of a plurality of splits used by a first test contains at least one resource that is shared, wherein the first test and a second test are sequenced for execution in two separate concurrently executing test flows. The method further comprises determining if the first test should execute before the second test if the split is associated with resources required by both the second and first tests. Finally the method comprises reserving the split containing the at least one shared resource for access by the first test before beginning execution of the first test.

Abstract: A method for performing tests using automated test equipment (ATE) is presented. The method comprises obtaining information concerning a test class using a graphical user interface. Further, it comprises generating a first header file automatically, wherein the first header file comprises the information concerning the test class. Next, it comprises importing the first header file into a test plan operable to execute using a tester operating system wherein the test plan comprises instances of the test class. It further comprises, generating a second header file from the first header file automatically, wherein the second header file is a header file for the test class. The method also comprises validating the test plan using the tester operating system. Finally, the method comprises loading the test plan and a compiled module onto the tester operating system for execution, wherein the compiled module is a compiled translation of the test class.

Abstract: A method for debugging test procedures for automated device testing is disclosed. The method comprises receiving a command to update at least one modified test procedure modified during a first debugging session and saving state information for a test plan, wherein the state information comprises information regarding a breakpoint entry location, and wherein the modified test procedure is invoked within the test plan. The method subsequently comprises suspending execution of the test plan and unloading the modified test procedure. It also comprises compiling the modified test procedure to produce a compiled file and then reloading the test procedure into the test plan using the compiled file. Finally, it comprises resuming execution of the modified test procedure in a second debugging session and breaking the execution during the second debugging session at a breakpoint corresponding to the breakpoint entry location.

Abstract: A method for using shared pins in a concurrent test execution environment is disclosed. The method relates to scheduling tests in concurrently executing test flows for automated test equipment (ATE) in a way so that resources can be shared between the test flows. The method comprises determining if any of a plurality of splits used by a first test contains at least one resource that is shared, wherein the first test and a second test are sequenced for execution in two separate concurrently executing test flows. The method further comprises determining if the first test should execute before the second test if the split is associated with resources required by both the second and first tests. Finally the method comprises reserving the split containing the at least one shared resource for access by the first test before beginning execution of the first test.

Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.

Abstract: Method and system for associating software components with vendor hardware module versions in an open architecture test system are disclosed. The method includes receiving a set of hardware versions of a vendor hardware module, receiving a set of software components supported by the vendor hardware module, processing the set of hardware versions, where the set of hardware versions is represented as an equivalence class of hardware version numbers using a mask value, obtaining user choices of hardware versions of the vendor hardware module, validating the user choices of hardware versions of the vendor hardware module, and creating a system profile in accordance with the user choices of hardware versions.

Abstract: A method for managing multiple hardware test module versions, software components, and tester operating system (TOS) versions in a modular test system is disclosed. The method includes installing the TOS versions compatible with the modular test system in an archive and installing vendor software components corresponding to the hardware test module versions in the archive. The method further includes creating system profiles for describing vendor software components corresponding to the hardware test module versions and the TOS versions, selecting a system profile for the modular test system, where the system profile includes a set of compatible vendor software components and a selected TOS for testing a particular hardware test module version, and activating the selected TOS on the modular test system.

Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.

Abstract: An efficient and low-cost method for testing multiple DUTs in a parallel test system is disclosed. In one embodiment, a method for scheduling tests in a parallel test system having at least two devices-under-test (DUTs) coupled to a test controller through one or more vendor hardware modules includes receiving a test plan comprising a plurality of tests arranged in a predetermined test flow, where the predetermined test flow comprises a plurality of tests arranged in a directed graph and each test is arranged as a vertex in the directed graph, determining a test execution schedule in accordance with the test plan at runtime, where the test execution schedule identifies a set of next tests to be executed according to current states of the at least two DUTs and where the set of next tests include different tests to be performed on different DUTs, and testing the at least two DUTs using the test execution schedule.

Abstract: A distributed operating system for a semiconductor test system, such as automated test equipment (ATE), is described. The operating system includes a host operating system for enabling control of one or more site controllers by a system controller. One or more local operating systems, each associated with a site controller, enable control of one or more test modules by an associated site controller. Each test module performs testing on a corresponding device-under-test at a test site.

Abstract: A method for communicating test information from a source to a destination is disclosed. The method includes providing a modular test system, where the modular test system comprises a system controller for controlling at least one site controller, the at least one site controller for controlling at least one test module. The method further includes providing a datalog framework for supporting extension of user-defined datalog formats, providing support classes for supporting user-initiated datalog events, receiving a datalog event requesting for communicating input test information from the source to the destination, configuring output test information based upon the destination, the datalog framework and the support classes, and transferring the output test information to the destination.

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of

Abstract: A method for managing a pattern object file in a modular test system is disclosed. The method includes providing a modular test system, where the modular test system comprises a system controller for controlling at least one site controller, and where the at least one site controller controls at least one test module and its corresponding device under test (DUT). The method further includes creating an object file management framework for establishing a standard interface between vendor-supplied pattern compilers and the modular test system, receiving a pattern source file, creating a pattern object metafile based on the pattern source file using the object file management framework, and testing the device under test through the test module using the pattern object metafile.

Abstract: A method for simulating a modular test system is disclosed. The method includes providing a controller, where the controller controls at least one vendor module and its corresponding device under test (DUT) model, creating a simulation framework for establishing standard interfaces between the at least one vendor module and its corresponding DUT model, configuring the simulation framework, and simulating the modular test system using the simulation framework.

Abstract: A method for developing a test program for a semiconductor test system is disclosed. The method includes describing a test plan file in a test program language (TPL), where the test plan file describes at least one test of the test program, describing a test class file in a system program language (SPL) and a corresponding pre-header file of the test class file in the TPL, where the test class file describes an implementation of the at least one test of the test program, and generating the test program using the test plan file, the test class file, and the pre-header file.

Abstract: A method for integrating test modules in a modular test system includes creating component categories for integrating vendor-supplied test modules and creating a calibration and diagnostics (C&D) framework for establishing a standard interface between the vendor-supplied test modules and the modular test system, where the C&D framework comprises interface classes communicating vendor-supplied module integration information. The method further includes receiving a vendor-supplied test module, retrieving module integration information from the vendor-supplied test module in accordance with the component categories, and integrating the vendor-supplied test module into the modular test system based on the module integration information using the C&D framework.

Abstract: A test method for debugging failures of an IC device with use of an event based semiconductor test system is capable of distinguishing a timing related failure from other failures. The test method includes the steps of: applying a test signal to a DUT and evaluating a response output of the DUT, detecting a failure in the response output, identifying a reference clock signal related to the failure, identifying a portion of the reference clock signal that is directly related to the failure, and incrementally changing a timing of events for the identified portion of the reference clock signal to detect change in the response output from the DUT.