Patents by Inventor Ankesh Jain

Ankesh Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8093929
    Abstract: A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: January 10, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ankesh Jain, Deependra Jain, Krishna Thakur
  • Publication number: 20110215842
    Abstract: A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module.
    Type: Application
    Filed: March 2, 2010
    Publication date: September 8, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Ankesh Jain, Deependra K. Jain, Krishna Thakur
  • Patent number: 7834657
    Abstract: An inverter circuit has a digital signal amplitude converter having an input coupled to an inverter circuit input node, and an amplitude converter output. A positive threshold voltage compensation generator has a positive threshold voltage compensation generator input coupled to the amplitude converter output. A negative threshold voltage compensation generator has a negative threshold voltage compensation generator input coupled to the inverter circuit input node, and a negative threshold voltage compensation generator output. A multiplexer has a first input coupled to the positive threshold voltage compensation generator output, a second input, coupled to the negative threshold voltage compensation generator output, and a multiplexer output. An inverter module has an output providing an inverter circuit output node, and an inverter module input is coupled to the multiplexer output.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: November 16, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sunny Arora, Mukesh Bansal, Dipesh K. Gupta, Ankesh Jain, Gaurav Jain, Ritika Singh