Abstract: According to one general aspect, an apparatus may include a register circuit and an instruction scheduler circuit. The register circuit may include a plurality of physical registers that are partitioned into at least a common portion that is associated with a predefined plurality of instructions, and a shared portion, and a plurality of write ports, wherein each portion is associated with at least one respective write port. The instruction scheduler circuit configured to determine an instruction, and rename an architectural register associated with the instruction to a physical register. Wherein the portion including the physical register is selected based, at least in part, upon a characteristic of the current instruction.

Abstract: According to one general aspect, an apparatus may include a cache pre-fetcher configured to predict data to be retrieved from a memory system. The cache pre-fetcher may include a pattern predictor circuit and a confirmation queue circuit. The pattern predictor circuit may be configured to predict a series of memory addresses to be pre-fetched from the memory system. The confirmation queue circuit may be configured to: maintain a windowed confirmation queue of predicted memory addresses, compare a requested memory address against the predicted memory addresses, and, if the requested memory address is included in the predicted memory addresses, indicate that a successful pre-fetch has occurred.

Abstract: According to one general aspect, an apparatus may include a cache pre-fetcher configured to predict data to be retrieved from a memory system. The cache pre-fetcher may include a pattern predictor circuit and a confirmation queue circuit. The pattern predictor circuit may be configured to predict a series of memory addresses to be pre-fetched from the memory system. The confirmation queue circuit may be configured to: maintain a windowed confirmation queue of predicted memory addresses, compare a requested memory address against the predicted memory addresses, and, if the requested memory address is included in the predicted memory addresses, indicate that a successful pre-fetch has occurred.

Abstract: According to one general aspect, an apparatus may include a register circuit and an instruction scheduler circuit. The register circuit may include a plurality of physical registers that are partitioned into at least a common portion that is associated with a predefined plurality of instructions, and a shared portion, and a plurality of write ports, wherein each portion is associated with at least one respective write port. The instruction scheduler circuit configured to determine an instruction, and rename an architectural register associated with the instruction to a physical register. Wherein the portion including the physical register is selected based, at least in part, upon a characteristic of the current instruction.

Abstract: A method includes identifying, at a scheduling unit, a resource conflict at a shared processing resource that is accessible by a first processing cluster and by a second processing cluster, where the first processing cluster, the second processing cluster, and the shared processing resource are included in a very long instruction word (VLIW) processing unit. The method also includes resolving the resource conflict.

Abstract: A method includes identifying, at a scheduling unit, a resource conflict at a shared processing resource that is accessible by a first processing cluster and by a second processing cluster, where the first processing cluster, the second processing cluster, and the shared processing resource are included in a very long instruction word (VLIW) processing unit. The method also includes resolving the resource conflict.

Abstract: A method and system for detecting and estimating noise in a video signal. For example, detail edges may be identified in a plurality of pixels, wherein each detail edge has an edge magnitude value. The detail edges in the plurality of pixels may be identified by: determining one or more directionality values for the plurality of pixels by passing the input video signal through at least one directional filter, and identifying the detail edges by assigning edge magnitude values based on whether the one or more directionality values exceed predetermined threshold levels. An edge map of the detail edges may be created, where the edge map is configured to indicate areas of the plurality of pixels to be considered or ignored in estimating the noise in the input video signal. The noise in the input video signal may then be estimated based on the indicated areas of the edge map.

Abstract: A method and system for detecting and estimating noise in a video signal. For example, with a video signal containing low power Gaussian noise, identifying a low-activity region in the input video signal, in which the pixels in the identified region have magnitude values within a range, and creating a histogram from the pixels in the identified region. Once a minimum number of pixels have been sorted into the histogram, estimating the standard deviation on the magnitude values of the pixels to estimate the noise that should be removed from the signal. An edge map or a binary map indicating pixels for inclusion in the estimation may be used to aid in the detection of low-activity regions of the input video signal.