Abstract: Multi-stage charge pumps use a modular structure in which each stage include a pair of legs, or current paths, between the stage input and the stage output. Each leg includes a stage boosting capacitor having a first plate connected to the current path and a second plate connected to receive one of a pair of non-overlapping clock signals. Each leg has an NMOS charge transfer switch connected between the stage input and the first plate of the stage boosting capacitor and a PMOS charge transfer switch connected between the first plate of the stage boosting capacitor and the stage output. To reduce charge pump area, the NMOS and PMOS charge transfer switches are formed to have a same resistance value when in an on state, where to achieve this the NMOS charge transfer switches are formed with wider control gates than the PMOS charge transfer switches.

Abstract: The application generally discloses systems and methods of generating a voltage waveform having an amplitude three times an input voltage amplitude using a plurality of low voltage (LV) triple well (TWL) N-type field effect devices. The method includes: receiving a first input voltage at a first input of a double switch charge transfer switch (CTS) circuit; applying a 2× kick voltage to a first capacitor coupled to a first portion of the double switch CTS circuit, the first capacitor configured to discharge a kick voltage to a source of a first LV TWL N-type field effect device; and applying a 1× kick voltage to a second capacitor coupled a second portion of the double switch CTS circuit, the second capacitor configured to discharge a kick voltage to a source of a second LV TWL N-type field effect device.

Abstract: Control circuits are configured to receive an input voltage through bond pads located on a surface of a die and generate supply voltages from the input voltage in a plurality of charge pumps located in a charge pump area of the die. The control circuits are further configured to provide the supply voltages to a plurality of voltage regulation circuits, each voltage regulation circuit located in a respective area of the die that corresponds to a portion of the nonvolatile memory array and generate a plurality of corresponding regulated voltages at each of the plurality of voltage regulation circuits for the corresponding portion of the nonvolatile memory array.

Abstract: Multi-stage charge pumps use a modular structure in which each stage include a pair of legs, or current paths, between the stage input and the stage output. Each leg includes a stage boosting capacitor having a first plate connected to the current path and a second plate connected to receive one of a pair of non-overlapping clock signals. Each leg has an NMOS charge transfer switch connected between the stage input and the first plate of the stage boosting capacitor and a PMOS charge transfer switch connected between the first plate of the stage boosting capacitor and the stage output. To reduce charge pump area, the NMOS and PMOS charge transfer switches are formed to have a same resistance value when in an on state, where to achieve this the NMOS charge transfer switches are formed with wider control gates than the PMOS charge transfer switches.

Abstract: A stage-based frequency optimization for a charge pump achieves a higher area efficiency by operating different stages of the charge pump at their optimized frequency simultaneously, instead of single common frequency, to obtain greater output strength. A first set of stages uses triple well devices as transfer switches and operates at a first, higher frequency. The first stages supply a second set of stages using high voltage devices as transfer switches and operates at a second, lower frequency. The two set of stages are connected through a frequency transition circuit.

Abstract: A stage-based frequency optimization for a charge pump achieves a higher area efficiency by operating different stages of the charge pump at their optimized frequency simultaneously, instead of single common frequency, to obtain greater output strength. A first set of stages uses triple well devices as transfer switches and operates at a first, higher frequency. The first stages supply a second set of stages using high voltage devices as transfer switches and operates at a second, lower frequency. The two set of stages are connected through a frequency transition circuit.

Abstract: The application generally discloses systems and methods of generating a voltage waveform having an amplitude three times an input voltage amplitude using a plurality of low voltage (LV) triple well (TWL)N-type field effect devices. The method includes: receiving a first input voltage at a first input of a double switch charge transfer switch (CTS) circuit; applying a 2× kick voltage to a first capacitor coupled to a first portion of the double switch CTS circuit, the first capacitor configured to discharge a kick voltage to a source of a first LV TWL N-type field effect device; and applying a 1× kick voltage to a second capacitor coupled a second portion of the double switch CTS circuit, the second capacitor configured to discharge a kick voltage to a source of a second LV TWL N-type field effect device.

Abstract: A hybrid charge pump is disclosed that employs novel arrangements of depletion-mode n-channel semiconductor devices and enhancement-mode p-channel semiconductor devices that eliminate or otherwise substantially reduce voltage drops that would otherwise occur across semiconductor device arrangements in existing charge pumps. As a result, the hybrid charge pump disclosed herein achieves the same output voltages as conventional charge pumps while requiring a reduced physical die area. Additionally, a hybrid charge pump arrangement disclosed herein employs a novel clocking scheme that reduces or eliminates reverse currents in the hybrid charge pump arrangement.

Abstract: A hybrid charge pump is disclosed that employs novel arrangements of depletion-mode n-channel semiconductor devices and enhancement-mode p-channel semiconductor devices that eliminate or otherwise substantially reduce voltage drops that would otherwise occur across semiconductor device arrangements in existing charge pumps. As a result, the hybrid charge pump disclosed herein achieves the same output voltages as conventional charge pumps while requiring a reduced physical die area. Additionally, a hybrid charge pump arrangement disclosed herein employs a novel clocking scheme that reduces or eliminates reverse currents in the hybrid charge pump arrangement.

Abstract: A charge pump includes first and second multiplier stages including first and second capacitor in series with an input node, a final multiplier stage including an output capacitor in series with the second capacitor and an output node, and pre-charge circuitry. The pre-charge circuitry is configured to charge the output capacitor to a first level during an initial phase of a charging operation, wherein the first level is equal to a supply voltage of the data storage system, and decouple a charging path of the pre-charge circuitry from the output capacitor in response to the output capacitor being charged to the first level. The first and second multiplier stages are configured to increase the charge of the output capacitor to second and third levels higher than the first level during second and third phases of the charging operation.