Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Abstract: A phase-locked loop (PLL) is implemented to have another (second) PLL in place of the controlled oscillator. When a known frequency change in the frequency of the output clock is desired, in addition to changing a configuration of the PLL (first PLL), the configuration of the second PLL is also changed to cause the frequency of the output clock to change quickly. In various embodiments, the configuration of the second PLL is changed by changing the divisor of the feedback divider of the second PLL, the divisor in a pre-scaler in the second PLL, the control voltage of a VCO used in the second PLL, and any other point of user control in the second PLL.

Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Abstract: An integrated circuit (IC) includes input/output (I/O) ports, each operating using one of a pair of unequal power supplies during normal operation of the IC. A lower supply of the pair of unequal power supplies is required to be used as the power supply for the I/O port when a first input signal to the IC is received from an external source on a first I/O port of the I/O ports. The voltage range of the logic excursions of the first input signal is greater than the range from a magnitude of the lower supply to a constant reference potential. A regulation loop derives a derived lower supply having a magnitude equaling that of the lower supply from the higher supply of the pair of unequal power supplies, and applies the derived lower supply on a power supply node of the first I/O port.

Abstract: A phase-locked loop (PLL) is implemented to have another (second) PLL in place of the controlled oscillator. When a known frequency change in the frequency of the output clock is desired, in addition to changing a configuration of the PLL (first PLL), the configuration of the second PLL is also changed to cause the frequency of the output clock to change quickly. In various embodiments, the configuration of the second PLL is changed by changing the divisor of the feedback divider of the second PLL, the divisor in a pre-scaler in the second PLL, the control voltage of a VCO used in the second PLL, and any other point of user control in the second PLL.

Abstract: A phase-locked loop (PLL) provided according to an aspect of the present disclosure includes a phase detector, a low-pass filter, an oscillator, an output block and a phase locking block. The oscillator generates an intermediate clock and the output block generates each of successive cycles of a feedback clock on counting a pre-determined number of cycles of the intermediate clock. The phase locking block, upon detecting the PLL being out of phase-lock, controls the operation of the output block to obtain phase-lock in the PLL within two cycles of the input clock from the time of detection of the PLL being out of phase-lock.

Abstract: A phase locked loop (PLL) includes a phase detector, a first low-pass filter, an oscillator, a feedback divider and a cycle slip detector. The cycle slip detector is operable to detect at a first time instance, a cycle slip between an input clock and a feedback clock of the PLL. Upon detection of the cycle slip, the cycle slip detector is operable to increase a loop BW of the PLL. As a result, faster relocking of the PLL is achieved upon occurrence of an abrupt and large frequency difference between the input clock and the feedback clock.

Abstract: A phase locked loop (PLL) includes a multiplexer (MUX), a phase detector, a filter block, an oscillator, a frequency divider, and a clock switch controller, and achieves hitless switching between a primary clock and a redundant clock. The clock switch controller, upon detecting a condition requiring switching from the primary clock to the redundant clock, is operable to restart the feedback divider synchronously with respect to the redundant clock, and derive the output of the PLL from the redundant clock. The PLL further includes a delay block to process delayed phase error signals generated by the phase detector. The PLL performs hitless clock switching in the event of input clock loss or in response to a command to switch input clocks. The PLL further includes circuitry for estimating and cancelling residual phase errors.

Abstract: A phase locked loop (PLL) includes a multiplexer (MUX), a phase detector, a filter block, an oscillator, a frequency divider, and a clock switch controller, and achieves hitless switching between a primary clock and a redundant clock. The clock switch controller, upon detecting a condition requiring switching from the primary clock to the redundant clock, is operable to restart the feedback divider synchronously with respect to the redundant clock, and derive the output of the PLL from the redundant clock. The PLL further includes a delay block to process delayed phase error signals generated by the phase detector. The PLL performs hitless clock switching in the event of input clock loss or in response to a command to switch input clocks. The PLL further includes circuitry for estimating and cancelling residual phase errors.

Abstract: A phase frequency detector (PFD) includes a first circuit portion and a second circuit portion. The first circuit portion receives a reference signal and activates a first error signal if the phase of the reference frequency leads the phase of a feedback signal. The second circuit portion receives the reference and activates a second error signal if the phase of the reference frequency lags the phase of the feedback signal. The first circuit portion is powered by a first power supply, and the second circuit portion is powered by a second power supply. A PLL implemented using the PFD generates a frequency output with minimized jitter.

Abstract: A low phase-noise phase locked loop (PLL). In an embodiment, the PLL includes a charge pump that includes a first switch, a second switch, a first resistor and a second resistor, which are connected in series. The first switch is provided between a power supply node and the first resistor, while the second switch is provided between the second resistor and a ground node. The junction of the first resistor and the second resistor provides the output of the charge pump. The first switch and the second switch are operated to be open or closed by outputs of a phase frequency detector of the PLL. In another embodiment, the charge pump and the low-pass filter of the PLL are implemented to process differential signals. Such implementation of the charge pump enables the PLL to generate an output signal with reduced phase-noise.

Abstract: A phase frequency detector (PFD) includes a first circuit portion and a second circuit portion. The first circuit portion receives a reference signal and activates a first error signal if the phase of the reference frequency leads the phase of a feedback signal. The second circuit portion receives the reference and activates a second error signal if the phase of the reference frequency lags the phase of the feedback signal. The first circuit portion is powered by a first power supply, and the second circuit portion is powered by a second power supply. A PLL implemented using the PFD generates a frequency output with minimized jitter.

Abstract: Systems and methods provide for a power management unit and its operation. The power management unit includes: a step-down power converter configured to receive a first voltage and output a second voltage, wherein the second voltage is less than the first voltage and at least one step-up power converter configured to receive the second voltage and output a third voltage, wherein the third voltage is greater than the second voltage. It also includes an inductive element connected to the step-down power converter and the at least one step-up power converter and configured to store energy and selectively release the stored energy, wherein the inductive element is time shared by both the step-down power converter and the at least one step-up power converter; and a finite state machine configured to control the time sharing of the inductive element.

Abstract: A device implementing a scheme for reduction of pop-up noise is disclosed. The device comprises an audio sub-system (100) having an integrator (112) for amplifying an input signal (133) and a modulation circuit (114) including one or more comparators. The audio subsystem (100) is further provided with a feedback loop (142) across the integrator (112) and the modulation circuit (114) to calibrate an offsets outputs of the integrator (112) and the modulation circuit (114). The feedback loop (142) includes an integrator-offset loop (202) across the integrator (112) to calibrate an offset (136) in the output of the integrator (112), and an offset calibration loop (302) across the modulation circuit (114) to calibrate an offset (140) in the output of the modulation circuit (114).

Abstract: A current controlling circuit comprises a DC power source, an inductor, a N-channel Metal Oxide Semiconductor (NMOS), one or more LEDs connected in series, a first resistor and a switching arrangement. The positive terminal of the DC power source is connected to the inductor in series. The series of LED is connected in series with the inductor and the first resistor. According to an embodiment the switching arrangement comprises a second resistor, a first switch and a second switch. The second resistor is connected in series with the second switch and connected in parallel with the first switch. The switching arrangement is connected in series with the first resistor and the negative terminal of the DC supply.

Abstract: A device and a method for implementing pulse width modulation for switching amplifiers (120) is described herein. In one embodiment, the device includes a sampling signal generator (202) to generate a sampling signal (208) and a modulation unit (102) operatively coupled to the sampling signal generator (202). The modulation unit (102) generates differential pulse width modulated waveforms based on the sampling signal (208) and differential input signals (220-1 and 220-2) such that at least one differential pulse width modulated waveform has a duty cycle equivalent to a pre-determined non-zero minimum pulse width at all values of the differential input signals (220-1 and 220-2).

Abstract: A device implementing a scheme for reduction of pop-up noise is disclosed. The device comprises an audio sub-system (100) having an integrator (112) for amplifying an input signal (133) and a modulation circuit (114) including one or more comparators. The audio subsystem (100) is further provided with a feedback loop (142) across the integrator (112) and the modulation circuit (114) to calibrate an offsets outputs of the integrator (112) and the modulation circuit (114). The feedback loop (142) includes an integrator-offset loop (202) across the integrator (112) to calibrate an offset (136) in the output of the integrator (112), and an offset calibration loop (302) across the modulation circuit (114) to calibrate an offset (140) in the output of the modulation circuit (114).

Abstract: A device and a method for implementing pulse width modulation for switching amplifiers (120) is described herein. In one embodiment, the device includes a sampling signal generator (202) to generate a sampling signal (208) and a modulation unit (102) operatively coupled to the sampling signal generator (202). The modulation unit (102) generates differential pulse width modulated waveforms based on the sampling signal (208) and differential input signals (220-1 and 220-2) such that at least one differential pulse width modulated waveform has a duty cycle equivalent to a pre-determined non-zero minimum pulse width at all values of the differential input signals (220-1 and 220-2).

Abstract: Systems and methods provide for a power management unit and its operation. The power management unit includes: a step-down power converter configured to receive a first voltage and output a second voltage, wherein the second voltage is less than the first voltage and at least one step-up power converter configured to receive the second voltage and output a third voltage, wherein the third voltage is greater than the second voltage. It also includes an inductive element connected to the step-down power converter and the at least one step-up power converter and configured to store energy and selectively release the stored energy, wherein the inductive element is time shared by both the step-down power converter and the at least one step-up power converter; and a finite state machine configured to control the time sharing of the inductive element.

Abstract: Traditionally, constant current source circuits (and, in particular, constant current source circuits that include cascoded current sources) had numerous drawbacks due to parasitic capacitances, especially at higher switching frequencies. Here, however, a constant current source circuit is provided which uses main and replica constant current source circuitry (with buffering therebetween) to counteract the problems created by parasitic capacitances. Thus, with these new circuits, a generally constant current can be generated, regardless of switching frequency.