Abstract: A quantized neural network circuit. The circuit may include a neuron processing element, the neuron processing element including a first neuron cluster and a second neuron cluster. The first neuron cluster may include: a first binary neuron, having a first input network with a first number of inputs; a second binary neuron, having a first input network with a second number of inputs, the second number being different from the first number; a plurality of multiplexers, each having an output connected to a respective input of the inputs of the first input network of the first binary neuron; and a plurality of flip-flops, each having an output connected to an input of a respective multiplexer of the plurality of multiplexers.

Abstract: A quantized neural network circuit. The circuit may include a neuron processing element, the neuron processing element including a first neuron cluster and a second neuron cluster. The first neuron cluster may include: a first binary neuron, having a first input network with a first number of inputs; a second binary neuron, having a first input network with a second number of inputs, the second number being different from the first number; a plurality of multiplexers, each having an output connected to a respective input of the inputs of the first input network of the first binary neuron; and a plurality of flip-flops, each having an output connected to an input of a respective multiplexer of the plurality of multiplexers.

Abstract: A system and method for clock distribution in a digital circuit. In some embodiments, the method, includes: modifying a synchronous digital logic circuit, the modifying including: replacing a first D flipflop in the circuit with a local-clocking source flipflop; and connecting a clock output of the local-clocking source flipflop to a clock input of a second D flipflop, wherein the replacing and connecting increases an objective function, the objective function being based on the number of high drive strength cells in a logic cone preceding the second D flipflop.

Abstract: A system and method for clock distribution in a digital circuit. In some embodiments, the method, includes: modifying a synchronous digital logic circuit, the modifying including: replacing a first D flipflop in the circuit with a local-clocking source flipflop; and connecting a clock output of the local-clocking source flipflop to a clock input of a second D flipflop, wherein the replacing and connecting increases an objective function, the objective function being based on the number of high drive strength cells in a logic cone preceding the second D flipflop.

Abstract: A system and method for computing in memory with artificial neurons. According to an embodiment of the present disclosure, there is provided a system, including: a computer-readable memory; a neuron processing element communicatively connected to the computer-readable memory, the neuron processing element including: a plurality of configurable processing circuits each having a plurality of outputs and a plurality of inputs; and a network connecting one or more of the outputs of the configurable processing circuits to one or more of the inputs of the configurable processing circuits, each of the configurable processing circuits including: an artificial neuron having a plurality of inputs; and a register connected to the inputs of the artificial neuron.

Abstract: Threshold logic gates using flash transistors are provided. In an exemplary aspect, flash threshold logic (FTL) provides a novel circuit topology for realizing complex threshold functions. FTL cells use floating gate (flash) transistors to realize all threshold functions of a given number of variables. The use of flash transistors in the FTL cell allows a fine-grained selection of weights, which is not possible in traditional complementary metal-oxide-semiconductor (CMOS)-based threshold logic cells. Further examples include a novel approach for programming the weights of an FTL cell for a specified threshold function using a modified perceptron learning algorithm.

Abstract: A field-programmable gate array (FPGA) with reconfigurable threshold logic gates for improved performance, power, and area (PPA) is provided. This disclosure describes a new architecture for an FPGA, referred to as threshold logic FPGA (TLFPGA), that integrates a conventional lookup table (LUT) with a complementary metal-oxide-semiconductor (CMOS) digital implementation of a binary perceptron, referred to as a threshold logic cell (TLC). The TLFPGA design described herein, combined with a new logic mapping algorithm that exploits the presence of both conventional LUTs and TLCs within the basic logic element (BLE) block, achieves significant improvements in all the metrics of PPA. The TLCs of embodiments described herein are capable of implementing a complex threshold function, which if implemented using conventional gates would require several levels of logic gates. The TLCs only require seven static random-access memory (SRAM) cells and are significantly faster than the conventional LUTs.

Abstract: A configurable binary neural network (BNN) application-specific integrated circuit (ASIC) using a network of programmable threshold logic standard cells is provided. A new architecture is presented for a BNN that uses an optimal schedule for executing the operations of an arbitrary BNN. This architecture, also referred to herein as TULIP, is designed with the goal of maximizing energy efficiency per classification. At the top-level, TULIP consists of a collection of unique processing elements (TULIP-PEs) that are organized in a single instruction, multiple data (SIMD) fashion. Each TULIP-PE consists of a small network of binary neurons, and a small amount of local memory per neuron. Novel algorithms are presented herein for mapping arbitrary nodes of a BNN onto the TULIP-PEs. Comparison results show that TULIP is consistently 3× more energy-efficient than conventional designs, without any penalty in performance, area, or accuracy.

Abstract: A field-programmable gate array (FPGA) with reconfigurable threshold logic gates for improved performance, power, and area (PPA) is provided. This disclosure describes a new architecture for an FPGA, referred to as threshold logic FPGA (TLFPGA), that integrates a conventional lookup table (LUT) with a complementary metal-oxide-semiconductor (CMOS) digital implementation of a binary perceptron, referred to as a threshold logic cell (TLC). The TLFPGA design described herein, combined with a new logic mapping algorithm that exploits the presence of both conventional LUTs and TLCs within the basic logic element (BLE) block, achieves significant improvements in all the metrics of PPA. The TLCs of embodiments described herein are capable of implementing a complex threshold function, which if implemented using conventional gates would require several levels of logic gates. The TLCs only require seven static random-access memory (SRAM) cells and are significantly faster than the conventional LUTs.