Abstract: A method of manufacturing a semiconductor device includes reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second first netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, the reducing errors including: inspecting a timing constraint list corresponding to the second netlist for addition candidates; generating a first version of the second netlist having a first number of comparison points relative to a logic equivalence check (LEC) context, the first number of comparison points being based on the addition candidates; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of electronic circuitry for an electronic device. The electronic device includes scan flip-flops to autonomously test the electronic circuitry for various manufacturing faults. The EDA of the present disclosure statistically groups the scan flip-flops into scan chains in such a manner such that scan flip-flops within each scan chain share similar characteristics, parameters, or attributes. Thereafter, the EDA of the present disclosure intelligently arranges ordering for the scan flip-flops within each of the scan chains to optimize power, performance, and/or area of the electronic circuitry.

Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.

Abstract: A method (of reducing errors in a migration a first netlist to a second netlist, the first and second netlists representing corresponding first and second implementations of a circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium), the method including: inspecting a timing constraint list for addition candidates, the timing constraint list corresponding to an initial netlist which represents the second implementation; relative to a logic equivalence check (LEC) context, increasing a number of comparison points based on the addition candidates, resulting in first version of the second netlist; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the first version of the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

Abstract: A method (of reducing errors in a migration a first netlist to a second netlist, the first and second netlists representing corresponding first and second implementations of a circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium), the method including: inspecting a timing constraint list for addition candidates, the timing constraint list corresponding to an initial netlist which represents the second implementation; relative to a logic equivalence check (LEC) context, increasing a number of comparison points based on the addition candidates, resulting in first version of the second netlist; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the first version of the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

Abstract: Methods and systems for determining a systematic defect in a circuit under test is provided. Elements of the circuit under test converted into scan cells. A first scan chain that includes a first plurality of scan cells is formed. Each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type. The first scan chain contains a first scan input and a first scan output. A first test pattern is applied at the scan input and a first test output is collected for the applied first test pattern at the first scan output. The collected first test output is compared with a first expected test output. The first cell type is marked to be a suspect for a systematic defect when the first test output is different from the first expected test output.

Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.

Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.

Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.

Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of electronic circuitry for an electronic device. The electronic device includes scan flip-flops to autonomously test the electronic circuitry for various manufacturing faults. The EDA of the present disclosure statistically groups the scan flip-flops into scan chains in such a manner such that scan flip-flops within each scan chain share similar characteristics, parameters, or attributes. Thereafter, the EDA of the present disclosure intelligently arranges ordering for the scan flip-flops within each of the scan chains to optimize power, performance, and/or area of the electronic circuitry.

Abstract: Methods and systems for determining a systematic defect in a circuit under test is provided. Elements of the circuit under test converted into scan cells. A first scan chain that includes a first plurality of scan cells is formed. Each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type. The first scan chain contains a first scan input and a first scan output. A first test pattern is applied at the scan input and a first test output is collected for the applied first test pattern at the first scan output. The collected first test output is compared with a first expected test output. The first cell type is marked to be a suspect for a systematic defect when the first test output is different from the first expected test output.

Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.