Patents by Inventor Ankitha M

Ankitha M has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260121652
    Abstract: Embodiments disclosed herein relate to digital signal processing, and more particularly, to detecting metastability to reduce noise and improve performance of an analog-to-digital converter (ADC). In an example, an ADC is provided that includes comparator circuitry, synchronization circuitry, digital output circuitry, and stability checking circuitry. The comparator circuitry performs a comparison of an analog input signal to an analog feedback signal and outputs a result of the comparison. The synchronization circuitry samples the result of the comparison at different times, resulting in first and second sampled values. The digital output circuitry generates a digital output signal based on the first sampled value and outputs the digital output signal. The stability checking circuitry determines whether a metastability condition occurred with respect to the analog-to-digital converter based on the first and second sampled values and outputs an indication of whether the metastability condition occurred.
    Type: Application
    Filed: October 30, 2024
    Publication date: April 30, 2026
    Inventors: Aniruddha Periyapatna Nagendra, Ashlesha Yerramsetty, Atul Lele, Meghna Agrawal, Venkatesh Kadlimatti, Dhivya Ravichandran, Ankitha M
  • Publication number: 20250330088
    Abstract: A technique for load monitoring. The technique includes measuring a first time period indicating an amount of time for recharging and discharging the charging circuit for a predetermined number of recharge cycles. The technique also includes measuring a second time period indicating a total amount of time in the predetermined number of recharge cycles. The technique further includes determining a duty cycle based on the first time period and the second time period and adjusting an inductor peak current circuit based on the determined duty cycle.
    Type: Application
    Filed: April 23, 2024
    Publication date: October 23, 2025
    Inventors: Venkatesh Kadlimatti, Ankitha M, Aniruddha Periyapatna Nagendra
  • Publication number: 20230138906
    Abstract: This disclosure relates to a system that includes a centralized trim controller and a non-volatile memory that includes a trim sector configured for hosting trim data for one or more peripherals. The trim controller is configured to receive, for each of the one or more peripherals, trim values of the one or more peripherals from the trim sector of the nonvolatile memory, and provide the trim values to the one or more peripherals. Some trim values are updateable by receiving a password at the trim controller. If the password is valid, a timeout counter is initiated, during which time the trim value is updateable.
    Type: Application
    Filed: December 30, 2021
    Publication date: May 4, 2023
    Inventors: Robin Osa HOEL, Anand Kumar G, Praveen KUMAR N, Aniruddha PERIYAPATNA NAGENDRA, Ankitha M