Patents by Inventor Ankitkumar Babariya
Ankitkumar Babariya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11037631Abstract: Strings of non-volatile memory cells include one or more joint regions adjacent to dummy non-volatile memory cells. During erase operations, different voltage levels are used for different dummy word lines coupled to respective dummy non-volatile memory cells. For example, a selection circuit may set a voltage level of a particular dummy word line to a voltage level greater than a different dummy word line. In another example, the selection circuit may determine a voltage level for a given dummy word line based on a distance between a non-volatile memory cell coupled to the given dummy word line and a selection device included in a string of non-volatile memory cells. Electron holes generated using the dummy word lines during erase operations may neutralize undesired trapped charges in a non-volatile memory string, thereby reducing disparity in erase times for different strings in the non-volatile memory circuit.Type: GrantFiled: January 18, 2019Date of Patent: June 15, 2021Assignee: Sandisk Technologies LLCInventors: Jayavel Pachamuthu, Amul Dhirajbhai Desai, Ankitkumar Babariya
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Publication number: 20200013469Abstract: Strings of non-volatile memory cells include one or more joint regions adjacent to dummy non-volatile memory cells. During erase operations, different voltage levels are used for different dummy word lines coupled to respective dummy non-volatile memory cells. For example, a selection circuit may set a voltage level of a particular dummy word line to a voltage level greater than a different dummy word line. In another example, the selection circuit may determine a voltage level for a given dummy word line based on a distance between a non-volatile memory cell coupled to the given dummy word line and a selection device included in a string of non-volatile memory cells. Electron holes generated using the dummy word lines during erase operations may neutralize undesired trapped charges in a non-volatile memory string, thereby reducing disparity in erase times for different strings in the non-volatile memory circuit.Type: ApplicationFiled: January 18, 2019Publication date: January 9, 2020Inventors: Jayavel Pachamuthu, Amul Dhirajbhai Desai, Ankitkumar Babariya
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Patent number: 10276251Abstract: A memory system performs verification when writing to memory. It is possible that the memory system may be missing some components (or components may be otherwise unavailable). To account for missing or unavailable components when performing verification, the memory system uses a pattern of data that includes a mask identifying the missing or unavailable components. The mask is used to force a predetermined result of the verification for the missing or unavailable portions of the memory structure so that results of the verification that correspond to the missing or unavailable components are not counted as errors.Type: GrantFiled: December 21, 2017Date of Patent: April 30, 2019Assignee: SanDisk Technologies LLCInventors: Sukhminder Singh Lobana, Kirubakaran Periyannan, Ankitkumar Babariya
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Patent number: 9830998Abstract: A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns. The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages. In one embodiment, the test may comprise programming a memory cell in each vertical column with data that matches the pattern of stress voltages, reading from the memory cells and determining whether data read matches data programmed. The applying of the stress voltages and the testing can be performed as part of a test during manufacturing or in the field during user operation.Type: GrantFiled: May 19, 2015Date of Patent: November 28, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Jayavel Pachamuthu, Sagar Magia, Ankitkumar Babariya, Jagdish Sabde
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Patent number: 9564219Abstract: For a non-volatile memory device having a NAND type of architecture, techniques are presented for determining NAND strings that are slow to program, including comparing the amount of current drawn by different sets of memory cells during different write operations. These techniques are particularly applicable to memory devices have a 3D structure, such as of BiCS type, where the slow programming can arise from defects of the spacing between the memory holes, in which the NAND strings are formed, and the local interconnects, such as for connecting common source lines and which run in a vertical direction between groups of NAND strings. The slow to program NAND strings can be recorded and this information can be used when writing data to the NAND strings. Several methods of writing data along a word line that includes such slow to program cells are described.Type: GrantFiled: April 8, 2015Date of Patent: February 7, 2017Assignee: SanDisk Technologies LLCInventors: Sagar Magia, Jagdish Sabde, Jayavel Pachamuthu, Ankitkumar Babariya
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Publication number: 20160343454Abstract: A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages. In one embodiment, the test may comprise programming a memory cell in each vertical column with data that matches the pattern of stress voltages, reading from the memory cells and determining whether data read matches data programmed. The applying of the stress voltages and the testing can be performed as part of a test during manufacturing or in the field during user operation.Type: ApplicationFiled: May 19, 2015Publication date: November 24, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Jayavel Pachamuthu, Sagar Magia, Ankitkumar Babariya, Jagdish Sabde
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Publication number: 20160300607Abstract: For a non-volatile memory device having a NAND type of architecture, techniques are presented for determining NAND strings that are slow to program, including comparing the amount of current drawn by different sets of memory cells during different write operations. These techniques are particularly applicable to memory devices have a 3D structure, such as of BiCS type, where the slow programming can arise from defects of the spacing between the memory holes, in which the NAND strings are formed, and the local interconnects, such as for connecting common source lines and which run in a vertical direction between groups of NAND strings. The slow to program NAND strings can be recorded and this information can be used when writing data to the NAND strings. Several methods of writing data along a word line that includes such slow to program cells are described.Type: ApplicationFiled: April 8, 2015Publication date: October 13, 2016Inventors: Sagar Magia, Jagdish Sabde, Jayavel Pachamuthu, Ankitkumar Babariya
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Patent number: 9269446Abstract: For a non-volatile memory device having a NAND type of architecture, techniques are presented for determining NAND strings that are slow to program. These techniques are particularly applicable to memory devices have a 3D structure, such as of BiCS type, where the slow programming can arise from defects of the spacing between the memory holes, in which the NAND strings are formed, and the local interconnects, such as for connecting common source lines and which run in a vertical direction between groups of NAND strings. The slow to program NAND strings can be recorded and this information can be used when writing data to the NAND strings. Several methods of writing data along a word line that includes such slow to program cells are described.Type: GrantFiled: April 8, 2015Date of Patent: February 23, 2016Assignee: SanDisk Technologies Inc.Inventors: Sagar Magia, Jagdish Sabde, Jayavel Pachamuthu, Ankitkumar Babariya