Patents by Inventor Ankur Ankur

Ankur Ankur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11974062
    Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: April 30, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Mihir Narendra Mody, Brijesh Jadav, Gang Hua, Niraj Nandan, Rajasekhar Reddy Allu, Ankur Ankur, Mayank Mangla
  • Patent number: 11941036
    Abstract: Logic may provide a hierarchical label structure for a document with a predicted set of hierarchical labels. Logic may provide a historical label performance database comprising performance data associated with each assignee in a complete set of assignees for each label in a complete set of the hierarchical labels. Logic may generate a first vector for the hierarchical label structure for the document. Logic may generate a second vector for the assignees in an identified set of assignees, comprising each hierarchical label in the predicted set of hierarchical labels for the document, the identified set comprising one or more of the assignees in the complete set of assignees. Logic may perform a similarity search to identify a predicted assignee from the identified set of assignees and logic may predict a selected assignee of the identified set of assignees to associate with the document via the similarity search.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: March 26, 2024
    Assignee: Capital One Services, LLC
    Inventors: Brian Nguyen, Paul Cho, Ankur Ankur
  • Publication number: 20240055004
    Abstract: Methods and systems for propagating a stopping condition through a multiple-producer, multiple-consumer distributed system. The method includes determining the number of active processes in a process layer, determining that a stopping condition is satisfied, generating a sentinel in a source queue, receiving a processing task at a process, determining whether the processing task is a sentinel, terminating the first process, decrementing the number of active processes by one, and generating the sentinel in a destination queue.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 15, 2024
    Applicant: Capital One Services, LLC
    Inventor: Ankur ANKUR
  • Publication number: 20230394075
    Abstract: Logic may provide a hierarchical label structure for a document with a predicted set of hierarchical labels. Logic may provide a historical label performance database comprising performance data associated with each assignee in a complete set of assignees for each label in a complete set of the hierarchical labels. Logic may generate a first vector for the hierarchical label structure for the document. Logic may generate a second vector for the assignees in an identified set of assignees, comprising each hierarchical label in the predicted set of hierarchical labels for the document, the identified set comprising one or more of the assignees in the complete set of assignees. Logic may perform a similarity search to identify a predicted assignee from the identified set of assignees and logic may predict a selected assignee of the identified set of assignees to associate with the document via the similarity search.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Applicant: Capital One Services, LLC
    Inventors: Brian NGUYEN, Paul CHO, Ankur ANKUR
  • Publication number: 20230385114
    Abstract: A data processing device includes a plurality of hardware accelerators, a scheduler circuit, and a blocking circuit. The scheduler circuit is coupled to the plurality of hardware accelerators, and includes a plurality of hardware task schedulers. Each hardware task scheduler is coupled to a corresponding hardware accelerator, and is configured to control execution of the task by the hardware accelerator. The blocking circuit is coupled to the plurality of hardware accelerators and configured to inhibit communication between a first hardware accelerator and a second hardware accelerator of the plurality of hardware task schedulers.
    Type: Application
    Filed: February 27, 2023
    Publication date: November 30, 2023
    Inventors: Mihir Mody, Niraj Nandan, Rajasekhar Allu, Ankur Ankur
  • Publication number: 20230291864
    Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 14, 2023
    Inventors: Mihir Narendra MODY, Brijesh JADAV, Gang HUA, Niraj NANDAN, Rajasekhar Reddy ALLU, Ankur ANKUR, Mayank MANGLA
  • Publication number: 20230267084
    Abstract: A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.
    Type: Application
    Filed: February 22, 2022
    Publication date: August 24, 2023
    Inventors: Mihir Narendra MODY, JR., Ankur ANKUR, Vivek Vilas DHANDE, Kedar Satish CHITNIS, Niraj NANDAN, Brijesh JADAV, Shyam JAGANNATHAN, Prithvi Shankar YEYYADI ANANTHA, Santhanakrishnan Narayanan NARAYANAN
  • Publication number: 20230196497
    Abstract: A technique including receiving an image stream for processing; processing the received image stream in a real time mode of operation; outputting an indication that an image processing pipeline has begun processing the received image stream; receiving, in response to the indication, first configuration information associated with test data for testing the image processing pipeline; switching the image processing pipeline to a non-real time mode of operation to process the test data based on the first configuration information during a vertical blanking period of the received image stream; loading the test data from an external memory; switching an input of the image processing pipeline from the image stream to the test data; determining a checksum based on the processed test data; comparing the determined checksum to an expected checksum to determine that the test data was successfully processed; and outputting an indication that the test data was successfully processed.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Inventors: Mihir Narendra MODY, Niraj NANDAN, Ankur ANKUR, Mayank MANGLA, Prithvi Shankar YEYYADI ANANTHA
  • Patent number: 10909715
    Abstract: A head tracking system uses coded features, highly structured compared to the operating environment, to ensure a high-integrity correspondence map. Coded features can be used to provide a negligible probability of spurious features and probability of misidentification. Ensuring a reliable correspondence map prevents unmodeled errors that arise from an invalid correspondence map. In the case of multiple outliers, existing screening techniques, such as random sample consensus (RANSAC) or fault exclusion, may be used to eliminate excessive outliers. Mature GPS integrity techniques may then be extended to optical pose estimation to establish integrity bounds for single faults that may go undetected by fault detection.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: February 2, 2021
    Assignee: Rockwell Collins, Inc.
    Inventors: Christopher M. Boggs, William T. Kirchner, Ankur Ankur
  • Publication number: 20100082330
    Abstract: Disclosed are methods and apparatus for supporting multi-lingual maps are disclosed. In one embodiment, a query indicating that a map is requested is received. A language in which the map is to be presented is determined. A set of map data for rendering the map is obtained, wherein the set of map data includes image data and text data. A translation of the text data in the set of map data is obtained such that the text data is translated to the language in which the map is to be presented. The image data and the translated text data are then provided.
    Type: Application
    Filed: September 29, 2008
    Publication date: April 1, 2010
    Inventors: Ankur Ankur, Xiang Wei Zhuo