Patents by Inventor Ankur Arya

Ankur Arya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10832965
    Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yiheng Xu, Haiting Wang, Qun Gao, Scott Beasor, Kyung Bum Koo, Ankur Arya
  • Patent number: 10593555
    Abstract: The manufacture of a FinFET device includes the formation of a composite sacrificial gate. The composite sacrificial gate includes a sacrificial gate layer such as a layer of amorphous silicon, and an etch selective layer such as a layer of silicon germanium. The etch selective layer, which underlies the sacrificial gate layer, enables the formation of a gate cut opening having a controlled critical dimension that extends through the composite sacrificial gate.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 17, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qun Gao, Naved Siddiqui, Ankur Arya, John R Sporre
  • Publication number: 20190295852
    Abstract: The manufacture of a FinFET device includes the formation of a composite sacrificial gate. The composite sacrificial gate includes a sacrificial gate layer such as a layer of amorphous silicon, and an etch selective layer such as a layer of silicon germanium. The etch selective layer, which underlies the sacrificial gate layer, enables the formation of a gate cut opening having a controlled critical dimension that extends through the composite sacrificial gate.
    Type: Application
    Filed: March 20, 2018
    Publication date: September 26, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Qun GAO, Naved SIDDIQUI, Ankur ARYA, John R. Sporre
  • Publication number: 20190214308
    Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 11, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yiheng Xu, Haiting Wang, Qun Gao, Scott Beasor, Kyung Bum Koo, Ankur Arya
  • Patent number: 10269932
    Abstract: One illustrative method disclosed herein includes, among other things, forming a first fin having first and second opposing sidewalls and forming a first sidewall spacer positioned adjacent the first sidewall and a second sidewall spacer positioned adjacent the second sidewall, wherein the first sidewall spacer has a greater height than the second sidewall spacer. In this example, the method further includes forming epitaxial semiconductor material on the fin and above the first and second sidewall spacers.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: April 23, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ankur Arya, Brian Greene, Qun Gao, Christopher Nassar, Junsic Hong, Vishal Chhabra