Abstract: At least one instruction storage coupled with a fetch unit including sets of fetch circuitry each having a same plurality of pipeline stages. The sets of fetch circuitry perform fetch operations to fetch blocks of instructions from the at least one instruction storage. Stall circuitry, in response to an indication of a hazard for a given pipeline stage of a first set of fetch circuitry, retains a fetch operation for a first block of instructions at the given pipeline stage, and zero or more fetch operations for zero or more corresponding blocks of instructions at zero or more preceding pipeline stages of the first set of fetch circuitry, until the hazard has been removed. The stall circuitry advances a fetch operation for a second block of instructions from the given pipeline stage of a second set of fetch circuitry, during an initial cycle of the one or more cycles.

Abstract: First and second instruction storage are coupled with a fetch unit including sets of fetch circuitry each spanning a plurality of pipeline stages. A first set of fetch circuitry is to initiates a fetch operation for a block of instructions, and has an indication to read the block of instructions from the second instruction storage. The first set retains the fetch operation for the block of instructions at a pipeline stage of the plurality, for one or more cycles, until a hazard corresponding to the pipeline stage of the first set of fetch circuitry has been removed. The first set stores the block of instructions from the second instruction storage to the first instruction storage, during the one or more cycles. The first set reads the block of instructions from the first instruction storage, for the fetch operation, once the hazard has been removed.

Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.