Abstract: A printed circuit board assembly having an edge joined first and second sub-circuit board is provided. The first sub-circuit board includes an edge with a stair-step profile interconnection wherein each of the stairs on the profile exposes an area of a signal layer. Each exposed portion of the signal layer has a plurality of signal pads thereon. The second sub-circuit board includes an edge with an inverse stair-step profile interconnection. A pad-on-pad connector is positioned in-between and electrically interconnects the respective signal layers on each sub-circuit board.

Abstract: A device to access and/or verify connections between a chip package and a printed circuit board (“PCB”), specifically within packages lacking back-side measurement access, includes a housing for insertion between the chip package and PCB. A passageway in the housing connects an entrance and an exit from the housing. The entrance is disposed on an end of the housing facing away from the chip package. The exit is disposed on a side of the housing below the chip package such that the passageway is directed at a signal path between the chip package and the PCB. A conductor disposed in the passageway is movable between a retracted position in which a contact end of the conductor is disposed within the passageway of the housing and an extended position in which the contact end of the conductor is disposed outside of the housing and in contact with the signal path.

Abstract: Disclosed herein is a method comprising drilling a first hole in a multilayered device; the multilayered device comprising a fill layer disposed between and in intimate contact with two layers of a first electrically conducting material; the fill layer being electrically insulating; plating the first hole with a slurry; the slurry comprising a magnetic material, an electrically conducting material, or a combination comprising at least one of the foregoing materials; filling the first hole with a fill material; the fill material being electrically insulating; laminating a first layer and a second layer on opposing faces of the multilayered device to form a laminate; the opposing faces being the faces through which the first hole is drilled; the first layer and the second layer each comprising a second electrically conducting material; drilling a second hole through the laminate; the second hole having a circumference that is encompassed by a circumference of the first hole; and plating the surface of the secon

Abstract: Methods and systems for controlled formation of a resist in a via. In one embodiment, a method for plating at least a portion of the inside of a via formed in an object may include filling the via with a resist capable of selective three-dimensional polymerization. The resist may be selectively polymerized, and developed. When the resist is developed, only a portion of the resist is removed according to whether the portion is polymerized, thereby leaving a remaining portion in the via and forming a desired structure in the via.