Patents by Inventor Ankush Bharati Oberai
Ankush Bharati Oberai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11763059Abstract: A defect map may be created by merging defects at locations on multiple dies that include copies of an integrated circuit (IC). Layout shapes or nets may be determined that overlap with the defects in the defect map. Next, connectivity between the layout shapes or nets may be determined. The defects may then be grouped into defect groups based on the connectivity between the layout shapes or nets, where each defect group comprises defects that overlap with layout shapes or nets that are electrically connected to each other.Type: GrantFiled: December 17, 2020Date of Patent: September 19, 2023Assignee: Synopsys, Inc.Inventors: Ankush Bharati Oberai, Rajesh Ramesh Sahani
-
Correlation between emission spots utilizing CAD data in combination with emission microscope images
Patent number: 11561256Abstract: A method includes capturing a photon emission microscope (PEM) image of an integrated circuit (IC), and identifying emission sites in the PEM image, where the emission sites are associated with a leakage current. A set of common nets is found that connects multiple emission sites using layout data and/or netlist data in computer-aided design (CAD) data. From the layout data and/or netlist data, a critical net is identified from the set of common nets connecting a threshold number of emission sites. The critical net is cross-mapped, by a processor, tip netlist data in the CAD data. A particular device is identified from the netlist data that has an output pin connected to the critical net. The particular device identified from the netlist data is cross-mapped, by a processor, to the layout data, wherein the critical net connects at least two devices at the identified emission sites including the particular device.Type: GrantFiled: December 28, 2020Date of Patent: January 24, 2023Assignee: Synopsys, Inc.Inventors: Ankush Bharati Oberai, Rupa Sunil Kamoji -
Correlation between Emission Spots Utilizing CAD Data in Combination with Emission Microscope Images
Publication number: 20210199714Abstract: A method includes capturing a photon emission microscope (PEM) image of an integrated circuit (IC), and identifying emission sites in the PEM image, where the emission sites are associated with a leakage current. A set of common nets is found that connects multiple emission sites using layout data and/or netlist data in computer-aided design (CAD) data. From the layout data and/or netlist data, a critical net is identified from the set of common nets connecting a threshold number of emission sites. The critical net is cross-mapped, by a processor, tip netlist data in the CAD data. A particular device is identified from the netlist data that has an output pin connected to the critical net. The particular device identified from the netlist data is cross-mapped, by a processor, to the layout data, wherein the critical net connects at least two devices at the identified emission sites including the particular device.Type: ApplicationFiled: December 28, 2020Publication date: July 1, 2021Applicant: Synopsys, Inc.Inventors: Ankush Bharati OBERAI, Rupa Sunil KAMOJI -
Publication number: 20210192116Abstract: A defect map may be created by merging defects at locations on multiple dies that include copies of an integrated circuit (IC). Layout shapes or nets may be determined that overlap with the defects in the defect map. Next, connectivity between the layout shapes or nets may be determined. The defects may then be grouped into defect groups based on the connectivity between the layout shapes or nets, where each defect group comprises defects that overlap with layout shapes or nets that are electrically connected to each other.Type: ApplicationFiled: December 17, 2020Publication date: June 24, 2021Applicant: Synopsys, Inc.Inventors: Ankush Bharati Oberai, Rajesh Ramesh Sahani
-
Patent number: 10990077Abstract: A method of performing virtual connectivity change between first and second nets associated with an integrated circuit is presented. The method includes generating a first top view and a first perspective views of a layout of the integrated circuit when a computer is invoked to perform the virtual connectivity change. The method further includes defining layers associated with the first and second nets, and defining a boundary of the virtual connectivity change. The method further includes performing the virtual connectivity change between the first and second nets within the boundary, and generating a second top view and a second perspective view of the layout of the integrated circuit after the virtual connectivity change.Type: GrantFiled: March 7, 2019Date of Patent: April 27, 2021Assignee: SYNOPSYS, INC.Inventor: Ankush Bharati Oberai
-
Patent number: 10650509Abstract: A method includes automatically aligning a laser-based timing analysis image of a semiconductor device with an image of a layout of the device. The method further includes controlling a speed at which a multitude of images subsequently obtained by the laser-based timing analysis are compared to the layout of the device to create a video overlay. The method further includes analyzing a multitude of potential failures of the semiconductor device by detecting movements of a multitude of hotspots on the layout as shown by the video overlay.Type: GrantFiled: September 8, 2017Date of Patent: May 12, 2020Assignee: SYNOPSYS, INC.Inventor: Ankush Bharati Oberai
-
Publication number: 20190302732Abstract: A method of performing virtual connectivity change between first and second nets associated with an integrated circuit is presented. The method includes generating a first top view and a first perspective views of a layout of the integrated circuit when a computer is invoked to perform the virtual connectivity change. The method further includes defining layers associated with the first and second nets, and defining a boundary of the virtual connectivity change. The method further includes performing the virtual connectivity change between the first and second nets within the boundary, and generating a second top view and a second perspective view of the layout of the integrated circuit after the virtual connectivity change.Type: ApplicationFiled: March 7, 2019Publication date: October 3, 2019Inventor: Ankush Bharati Oberai
-
Patent number: 10295988Abstract: A method of performing virtual connectivity change between first and second nets associated with an integrated circuit is presented. The method includes generating a first top view and a first perspective views of a layout of the integrated circuit when a computer is invoked to perform the virtual connectivity change. The method further includes defining layers associated with the first and second nets, and defining a boundary of the virtual connectivity change. The method further includes performing the virtual connectivity change between the first and second nets within the boundary, and generating a second top view and a second perspective view of the layout of the integrated circuit after the virtual connectivity change.Type: GrantFiled: August 31, 2017Date of Patent: May 21, 2019Assignee: Synopsys, Inc.Inventor: Ankush Bharati Oberai
-
Publication number: 20180068428Abstract: A method includes automatically aligning a laser-based timing analysis image of a semiconductor device with an image of a layout of the device. The method further includes controlling a speed at which a multitude of images subsequently obtained by the laser-based timing analysis are compared to the layout of the device to create a video overlay. The method further includes analyzing a multitude of potential failures of the semiconductor device by detecting movements of a multitude of hotspots on the layout as shown by the video overlay.Type: ApplicationFiled: September 8, 2017Publication date: March 8, 2018Inventor: Ankush Bharati Oberai
-
Publication number: 20180059643Abstract: A method of performing virtual connectivity change between first and second nets associated with an integrated circuit is presented. The method includes generating a first top view and a first perspective views of a layout of the integrated circuit when a computer is invoked to perform the virtual connectivity change. The method further includes defining layers associated with the first and second nets, and defining a boundary of the virtual connectivity change. The method further includes performing the virtual connectivity change between the first and second nets within the boundary, and generating a second top view and a second perspective view of the layout of the integrated circuit after the virtual connectivity change.Type: ApplicationFiled: August 31, 2017Publication date: March 1, 2018Inventor: Ankush Bharati Oberai