Abstract: Aspects of the disclosure are directed to allocating bandwidth. As may be implemented in accordance with one or more embodiments, respective amounts of bandwidth are allocated to respective application groups for each memory access cycle in a set of memory access cycles. Initial bonus bandwidth is provided to a first one of the application groups during one of the memory access cycles. The bonus bandwidth may include at least a portion of bandwidth allocated to and unused by one of the other respective application groups during the memory access cycle. Additional bonus bandwidth is selectively provided to the first application group during one of the memory access cycles based on the initial bonus bandwidth and a maximum amount of bonus bandwidth defined for the set of memory access cycles, in response to bandwidth allocated to one of the other respective application groups during the subsequent memory access cycle being unused.

Abstract: An aspect of the invention is directed towards a data processing system and method including a transaction scheduler configured to process transactions, a tag control circuit coupled to the transaction scheduler configured to detect a fault by comparing output signals, and a controller coupled to the tag control circuit. The controller is configured to receive a transaction request identifying a transaction, generate a unique tag value for the transaction request, load the unique tag value into the transaction scheduler, determine a current unique tag value associated with the transaction being executed, and generate a fault. The system is further configured to generate fault when: (i) the current unique tag value is not found, or (ii) the transactions timeout after a predetermined number of cycles.

Abstract: A system-on-chip (SoC) may include a plurality of terminals and a plurality of terminal controllers. Each terminal controller is configured to selectively disable a terminal. An SoC be configured to execute at least one application. An SoC may include a memory configured to store a plurality of terminal masks. Each terminal mask identifies a subset of the plurality of terminals to be disabled. An SoC may include a fault collection and reaction system configured to transmit, to the plurality of terminal controllers, a fault indication signal in response to an error in a corresponding application. Each terminal controller is further configured to determine, based on a fault indication signal and a value in a terminal mask, whether the terminal corresponding to the terminal controller is to be disabled, and when the terminal corresponding to the terminal controller is to be disabled, disable the terminal.

Abstract: A fault collection and reaction system on a system-on-chip (SoC) includes a plurality of reaction cores assigned to a plurality of applications being executed by a plurality of processor cores on the SoC, at least one look-up table (LUT), and a controller. The at least one LUT stores therein a first mapping between the plurality of reaction cores and corresponding plurality of domain identifiers, and a second mapping between a plurality of faults and a set of reaction combinations. The controller receives a fault indication and a first domain identifier in response to occurrence of a first fault and selects from the plurality of reaction cores, a first reaction core mapped to the first domain identifier, and from the set of reaction combinations, a first reaction combination mapped to the first fault. The first reaction core responds to the fault indication with a reaction based on the selected reaction combination.

Abstract: A device configured to periodically monitor operational activity of hardware components within a computing system infrastructure. The device is further configured to detect an issue that is associated with a hardware component, to identify commands that are sent to the hardware component to resolve the first issue, and to identify a test environment configuration for simulating the effect of sending the commands to the hardware component on the computing system infrastructure. The device is further configured to generate a solution script based on the identified commands and a testing script based on the identified test environment configuration, and to store an association between the first issue, the solution script, and the testing script in a script map.

Abstract: A fault collection and reaction system on a system-on-chip (SoC) includes a plurality of reaction cores assigned to a plurality of applications being executed by a plurality of processor cores on the SoC, at least one look-up table (LUT), and a controller. The at least one LUT stores therein a first mapping between the plurality of reaction cores and corresponding plurality of domain identifiers, and a second mapping between a plurality of faults and a set of reaction combinations. The controller receives a fault indication and a first domain identifier in response to occurrence of a first fault and selects from the plurality of reaction cores, a first reaction core mapped to the first domain identifier, and from the set of reaction combinations, a first reaction combination mapped to the first fault. The first reaction core responds to the fault indication with a reaction based on the selected reaction combination.

Abstract: A device configured to periodically monitor operational activity of hardware components within a computing system infrastructure. The device is further configured to detect an issue that is associated with a hardware component, to identify commands that are sent to the hardware component to resolve the first issue, and to identify a test environment configuration for simulating the effect of sending the commands to the hardware component on the computing system infrastructure. The device is further configured to generate a solution script based on the identified commands and a testing script based on the identified test environment configuration, and to store an association between the first issue, the solution script, and the testing script in a script map.

Abstract: A programming interface and method of operating a programming interface use a system clock input, an asynchronous reset input, and an interface control input. The method selectively controls multiplexed coupling of a source register to a destination register and the destination register to a buffer register. The multiplexed coupling of the destination register to the buffer register reduces the possibility of the buffer register being corrupted when an asynchronous reset signal is applied to the programming interface. Problems associated with meta-stable asynchronous crossing paths in asynchronous reset programming systems are therefore alleviated.

Abstract: A programming interface and method of operating a programming interface use a system clock input, an asynchronous reset input, and an interface control input. The method selectively controls multiplexed coupling of a source register to a destination register and the destination register to a buffer register. The multiplexed coupling of the destination register to the buffer register reduces the possibility of the buffer register being corrupted when an asynchronous reset signal is applied to the programming interface. Problems associated with meta-stable asynchronous crossing paths in asynchronous reset programming systems are therefore alleviated.