Patents by Inventor Ankush Varma
Ankush Varma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250208920Abstract: Disclosed are processor systems having cores with context registers to store priority information for threads to run on the core. They also include circuitry to change the core frequency for the thread based on the priority information.Type: ApplicationFiled: November 21, 2024Publication date: June 26, 2025Inventors: Adwait PURANDARE, Nikhil GUPTA, Andrew J. HERDRICH, Long CUI, Ankush VARMA, Stanley CHEN, Krishnakanth V. SISTLA, Yuval BUSTAN, Rami AMSIS, Ofer NATHAN, Eric J. DEHAEMER, Nilanjan PALIT, Shruthi VENUGOPAL
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Publication number: 20250199926Abstract: Techniques for monitoring the health of resource circuits are described.Type: ApplicationFiled: September 27, 2024Publication date: June 19, 2025Inventors: Vijay Anand MATHIYALAGAN, Vivek GARG, Ankush VARMA
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Publication number: 20250199931Abstract: Techniques and mechanisms for determining an operational state of a processor with inference engine circuitry. In an embodiment, inference engine circuitry implements a classification function with which a given workload is classified as belonging to any of multiple possible workload classes. Each of the workload classes corresponds to a different respective value of an uncore-core frequency ratio. The inference engine circuitry receives or otherwise identifies telemetry information which is generated during a particular phase of the workload execution. Based on the telemetry information, the inference engine circuitry generates an output specifying or otherwise indicating a recommended frequency ratio value which corresponds to an identified workload class. In another embodiment, a frequency of a core, or a frequency of uncore resource, is changed based on the recommended frequency ratio value.Type: ApplicationFiled: June 28, 2024Publication date: June 19, 2025Applicant: Intel CorporationInventors: Ujjwal Gupta, Sai Mahathi Naladala, Ankush Varma
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Patent number: 12314114Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.Type: GrantFiled: July 17, 2023Date of Patent: May 27, 2025Assignee: Intel CorporationInventors: Alexander Gendler, Efraim Rotem, Nir Rosenzweig, Krishnakanth V. Sistla, Ashish V. Choubal, Ankush Varma
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Patent number: 12298833Abstract: A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.Type: GrantFiled: June 26, 2020Date of Patent: May 13, 2025Assignee: Intel CorporationInventors: Ujjwal Gupta, Ankush Varma, Lakshmipriya Seshan, Nikethan Shivanand Baligar, Nikhil Gupta, Swadesh Choudhary, Yogesh Bansal
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Patent number: 12282377Abstract: A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.Type: GrantFiled: June 25, 2021Date of Patent: April 22, 2025Assignee: Intel CorporationInventors: Pritesh P. Shah, Suresh Chemudupati, Alexander Gendler, David Hunt, Christopher M. Macnamara, Ofer Nathan, Adwait Purandare, Ankush Varma
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Publication number: 20250076954Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.Type: ApplicationFiled: September 12, 2024Publication date: March 6, 2025Inventors: Vivek GARG, Ankush VARMA, Krishnakanth SISTLA, Nikhil GUPTA, Nikethan Shivanand BALIGAR, Stephen WANG, Nilanjan PALIT, Timothy Yee-Kwong KAM, Adwait PURANDARE, Ujjwal GUPTA, Stanley CHEN, Dorit SHAPIRA, Shruthi VENUGOPAL, Suresh CHEMUDUPATI, Rupal PARIKH, Eric DEHAEMER, Pavithra SAMPATH, Phani Kumar KANDULA, Yogesh BANSAL, Dean MULLA, Michael TULANOWSKI, Stephen Paul HAAKE, Andrew HERDRICH, Ripan DAS, Nazar Syed HAIDER, Aman SEWANI
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Publication number: 20250004495Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: ApplicationFiled: July 5, 2024Publication date: January 2, 2025Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
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Publication number: 20250004536Abstract: Techniques and mechanisms for determining operation a processor core which is in a common power delivery domain with one or more other processor cores. In an embodiment, an execution of instructions by a first core of a processor module is selectively throttled based on the detection of a single violation condition. The throttling is performed while the cores of the processor module are each maintained in a current power state. The single violation condition comprises a violation of a test criteria by the first core, while the one or more other cores of the module each satisfy the test criteria. In the case of a multiple violation condition, each core of the processor module is transitioned from one power state to another power state. In another embodiment, the test criteria includes or is otherwise based on a threshold level of a dynamic capacitance for a given core.Type: ApplicationFiled: June 29, 2023Publication date: January 2, 2025Applicant: Intel CorporationInventors: Adwait Purandare, Ankush Varma, Nilanjan Palit, Yuval Bustan, Eran Barnett, Eliezer Weissman, Stanley Chen, Arjan Van De Ven
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Patent number: 12124350Abstract: A scheme is provided for a processor to measure or estimate the dynamic capacitance (Cdyn) associated with an executing application and take a proportional throttling action. Proportional throttling has significantly less impact on performance and hence presents an opportunity to get back the lost bins and proportionally clip power if it exceeds a specification threshold. The ability to infer a magnitude of power excursion of a power virus event (and hence, the real Cdyn) above a set power threshold limit enables the processor to proportionally adjust the processor operating frequency to bring it back under the limit. With this scheme, the processor distinguishes a small power excursion versus a large one and reacts proportionally, yielding better performance.Type: GrantFiled: April 28, 2020Date of Patent: October 22, 2024Assignee: Intel CorporationInventors: Aman Sewani, Nazar Haider, Ankush Varma, Lan Vu
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Patent number: 12124314Abstract: An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (P0nMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.Type: GrantFiled: March 19, 2021Date of Patent: October 22, 2024Assignee: Intel CorporationInventors: Alexander Gendler, Adwait Purandare, Ankush Varma, Nazar Haider, Daniela Kaufman, Gilad Bomstein, Shlomo Attias, Amit Gabai, Ariel Szapiro
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Patent number: 12093100Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.Type: GrantFiled: September 26, 2020Date of Patent: September 17, 2024Assignee: Intel CorporationInventors: Vivek Garg, Ankush Varma, Krishnakanth Sistla, Nikhil Gupta, Nikethan Shivanand Baligar, Stephen Wang, Nilanjan Palit, Timothy Yee-Kwong Kam, Adwait Purandare, Ujjwal Gupta, Stanley Chen, Dorit Shapira, Shruthi Venugopal, Suresh Chemudupati, Rupal Parikh, Eric Dehaemer, Pavithra Sampath, Phani Kumar Kandula, Yogesh Bansal, Dean Mulla, Michael Tulanowski, Stephen Paul Haake, Andrew Herdrich, Ripan Das, Nazar Syed Haider, Aman Sewani
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Patent number: 12066853Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: GrantFiled: June 5, 2023Date of Patent: August 20, 2024Assignee: Intel CorporationInventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das
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Patent number: 11953962Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.Type: GrantFiled: December 22, 2022Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Daniel J. Ragland, Guy M. Therien, Ankush Varma, Eric J. DeHaemer, David T. Mayo, Ariel Gur, Yoav Ben-Raphael, Mark P. Seconi
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Patent number: 11899615Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.Type: GrantFiled: January 27, 2023Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z Chrysos, John R. Ayers, Dheeraj R. Subbareddy
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Patent number: 11886918Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.Type: GrantFiled: April 11, 2022Date of Patent: January 30, 2024Assignee: INTEL CORPORATIONInventors: Ankush Varma, Nikhil Gupta, Vasudevan Srinivasan, Krishnakanth Sistla, Nilanjan Palit, Abhinav Karhu, Eugene Gorbatov, Eliezer Weissmann
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Publication number: 20240028101Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.Type: ApplicationFiled: September 29, 2023Publication date: January 25, 2024Inventors: Jianwei Dai, David Pawlowski, Adwait Purandare, Ankush Varma
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Patent number: 11853144Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.Type: GrantFiled: May 19, 2022Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Jianwei Dai, David Pawlowski, Adwait Purandare, Ankush Varma
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Publication number: 20230359263Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.Type: ApplicationFiled: July 17, 2023Publication date: November 9, 2023Inventors: Alexander Gendler, Efraim Rotem, Nir Rosenzweig, Krishnakanth V. Sistla, Ashish V. Choubal, Ankush Varma
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Publication number: 20230315143Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.Type: ApplicationFiled: June 5, 2023Publication date: October 5, 2023Inventors: Vasudevan Srinivasan, Krishnakanth V. Sistla, Corey D. Gough, Ian M. Steiner, Nikhil Gupta, Vivek Garg, Ankush Varma, Sujal A. Vora, David P. Lerner, Joseph M. Sullivan, Nagasubramanian Gurumoorthy, William J. Bowhill, Venkatesh Ramamurthy, Chris MacNamara, John J. Browne, Ripan Das