Abstract: A system and method for controlling DRAM is described. According to exemplary embodiments of the present invention, a memory subsystem can be populated by end users with any of a variety of DRAM chips. A memory controller will size each memory bank and determine whether paired memory banks are to be configured as interleaved or non-interleaved based upon the detected DRAM population. Bank selection logic is designed to account for both size and status (interleaved or non-interleaved) when determining which memory bank contains a memory location of interest. Row and column addressing is selected to minimize decoding of an incoming system address and reduce DRAM access time.

Abstract: A system and method for controlling DRAM is described. According to exemplary embodiments of the present invention, a memory subsystem can be populated by end users with any of a variety of DRAM chips. A memory controller will size each memory bank and determine whether paired memory banks are to be configured as interleaved or non-interleaved based upon the detected DRAM population. Bank selection logic is designed to account for both size and status (interleaved or non-interleaved) when determining which memory bank contains a memory location of interest. Row and column addressing is selected to minimize decoding of an incoming system address and reduce DRAM access time.

Abstract: A system and method for changing an arbitration priority of a bus master are described. A changing system condition can be detected and used to signal the arbiter to change the priority of one or more bus masters. Timers can be provided to delay the request of a changed priority and to return a bus master to its default priority.