Patents by Inventor Ann Concannon

Ann Concannon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7929262
    Abstract: In a ESD protection device, hot carrier degradation and soft leakage are reduced by introducing a dynamic driver that includes a RC circuit for keeping the triggering circuit of the ESD device in an on-state for a certain period of time. This allows the current through the ESD protection device to be reduced during the RC delay time.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: April 19, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter Hopper, Ann Concannon
  • Patent number: 7387918
    Abstract: When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the collector of the NPN transistor between the emitter and collector of the PNP transistor.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: June 17, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Ann Concannon, Marcel Ter Beek
  • Patent number: 7268398
    Abstract: In an NMOS device, the turn-on voltage or the triggering voltage is reduced by adding an NBL connected to an n-sinker and contacted through an n+ region, which is connected to a bias voltage. The bias voltage may be provided by the drain contact or by a separate bias voltage.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: September 11, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper
  • Patent number: 7193251
    Abstract: In multiple port chip circuit, an ESD protection circuit and method of protecting the ports of the multiple port circuit, includes providing a plurality of bi-directional snapback devices such as DIACs and connecting only one electrode to ground while connecting the other electrodes to the ports that are to be protected.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: March 20, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J Hopper, Marcel ter Beek
  • Patent number: 7115951
    Abstract: In a triggering ESD protection structure, the triggering voltage is reduced by introducing one or more corners or spikes into the p-n breakdown junction. This may be done by providing a polygate with a zig-zag pattern to define triangular corners in the drain or anode of the structure.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: October 3, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek, Yuri Mirgorodsky
  • Patent number: 7064397
    Abstract: When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the collector of the NPN transistor between the emitter and collector of the PNP transistor.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: June 20, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Ann Concannon, Marcel Ter Beek
  • Patent number: 7057215
    Abstract: In an ESD protection device making use of a LVTSCR-like structure or an IGBT-like structure, negative polarity over-voltage protection is achieved by providing a LVTSCR-like structure or IGBT-like structure that defines a PMOS device.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: June 6, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek
  • Patent number: 7056761
    Abstract: In an avalanche structure, different breakdown voltages are achieved by making use of a polygate and forming a highly doped p-n junction beneath the polygate, and adjusting the gate length and optionally the bias voltage of the gate.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: June 6, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hoppet, Marcel ter Beek
  • Patent number: 7027278
    Abstract: A stacked high-voltage ESD protection clamp is provided that realizes the desired triggering characteristics of a BJT or BSCR stacked snapback clamp. The operational principle of the new circuit is based upon introduction of a middle node capacitor into the stacked (cascoded) clamp. The capacitor (or driver) provides conditions for a two-stage turn-on. At the beginning of an ESD pulse, the capacitor is discharged. With the ESD voltage increase, part of the current is used to charge the capacitor, thus shunting one of the BJTs (BSCRs). As a result, the other BJT (BSCR) will experience fast turn-on. After turn-on, the current provides a fast charge of the capacitor and the turn-on of the second device. Thus, the middle node capacitor allows the triggering characteristics of the clamp to be controlled.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: April 11, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Ann Concannon
  • Patent number: 7023029
    Abstract: In an ESD protection device using a SCR-like structure, a vertical device is provided that is highly robust and easily allows the triggering voltage to be adjusted during manufacture. Furthermore it is implementable in complementary form based on PNP and NPN BJT structures, to provide both positive and negative pulse protection.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: April 4, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek
  • Patent number: 6998651
    Abstract: In a LVTSCR-like structure, an additional p+ region is formed adjacent a n+ floating drain to define a p-n junction with the floating drain underneath a polygate of the structure. The polygate is used as a mask during doping of the p+ region and the n+ floating drain, and the length of the polygate is adjusted to provide the desired triggering voltage for the structure. The triggering voltage is also adjusted by biasing the polygate.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: February 14, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashohenko, Ann Concannon, Peter J. Hopper, Marcel Eer Beek
  • Patent number: 6970335
    Abstract: In an SCR-based ESD protection clamp, the voltage overshoot during an ESD event is reduced by separately controlling the voltage pulse to the drain and emitter contacts of the SCR. The voltage pulse to the drain is preferably delayed using a delay circuit such as an RC circuit. This allows double conductivity modulation to be achieved with lower voltage overshoot.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: November 29, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J Hopper, Marcel ter Beek
  • Patent number: 6952039
    Abstract: In a self protection I/O, a multiple gate NMOS structure is designed to shift the avalanche multiplication region away from the edge of the gate nearest the drain. This is achieved by providing a lightly doped region between the edge of the gate and the ballast region of the drain.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: October 4, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek
  • Patent number: 6946690
    Abstract: The holding voltage (the minimum voltage required for operation) of a LVTSCR-like device is increased to a value that is greater than a dc bias on a to-be-protected node. The holding voltage is increased by reducing the size of the p+ emitter defined by the LVTSCR-like device. As a result, the LVTSCR can be utilized to provide ESD protection to power supply pins, having better current capabilities than a GGNMOS and better holding voltage characteristics than a LVTSCR.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: September 20, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper
  • Patent number: 6933588
    Abstract: In a NPN transistor electrostatic discharge (ESD) protection structure, certain parameters, including maximum lattice temperature, are improved by introducing certain process changes to provide for SCR-like characteristics during ESD events. A p+region is formed adjacent the collector to define a SCR-like emitter and with a common contact with the collector of the BJT. The p+ region is spaced from the n-emitter of the transistor by a n-epitaxial region, and the collector is preferably spaced further from the n-emitter than is the case in a regular BJT.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: August 23, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek
  • Patent number: 6911679
    Abstract: In an ESD protection device making use of a LVTSCR, at least one contacted drain and at least one emitter are formed, and are arranged laterally next to each other to be substantially equidistant from the gate of the LVTSCR, to improve holding voltage and decrease size. The ratio of emitter width to contacted drain width is adjusted to achieve the desired characteristics.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: June 28, 2005
    Assignee: National Semiconductor Corp.
    Inventors: Vladislav Vashchenko, Ann Concannon, Marcel ter Beek, Peter J. Hopper
  • Patent number: 6906357
    Abstract: An apparatus including an electrostatic discharge (ESD) protection structure with a diac in which substancially similar ESD protection is provided for both positive and negative ESD voltages appearing at the circuit electrode sought to be protected.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: June 14, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Marcel ter Beek, Peter J. Hopper, Ann Concannon
  • Patent number: 6894881
    Abstract: In an ESD protection circuit, diodes for shunting current through an ESD clamp include a third terminal in order to provide a dual current path through the diode structure and provide for a voltage drop to the input of the protected internal circuit. In another embodiment, where a bipolar junction transistor is used as an ESD clamp to shunt current to ground between an I/O pad and an input to a protected internal circuit, a lower voltage is provided to the internal circuit by providing a voltage drop across an internal resistive element of the bipolar junction transistor. This is achieved by making use of two base terminals, one connected to the I/O pad, and the other connected to the input of the internal circuit and spaced from the first contact by the base polysilicon region of the bipolar junction transistor.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: May 17, 2005
    Assignee: National Semiconductor Corp
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper
  • Patent number: 6853053
    Abstract: In a BJT ESD protection structure, the ESD current density is stabilized by partially blocking one or more of the emitter and n+ collector, sinker, and n-buried layer to define a comb-like structure for the partially blocked regions.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: February 8, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek
  • Patent number: 6841829
    Abstract: In a BSCR and method of making a BSCR, a npn BJT structure is created and a p+ region is provided that is connected to the collector of the BJT, and one or more of the NBL, sinker and n+ collector of the BJT are partially blocked. In this way the NBL is formed into a comb-like NBL with a plurality of tines in one embodiment. The sinker and n+ collector may also be formed into a plurality islands. Furthermore, the period of the tines and islands may be varied to provide the desired BSCR characteristics.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: January 11, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek