Patents by Inventor Ann E. Huffman

Ann E. Huffman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for prediction of zero arithmetic/logic results
    Patent number: 4947359
    Abstract: The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.
    Type: Grant
    Filed: May 1, 1989
    Date of Patent: August 7, 1990
    Assignee: International Business Machines Corporation
    Inventors: Stamatis Vassiliadis, Michael Putrino, Ann E. Huffman, Brice J. Feal, Gerald G. Pechanek
  • Method and apparatus for modified carry-save determination of arithmetic/logic zero results
    Patent number: 4924422
    Abstract: The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.
    Type: Grant
    Filed: February 17, 1988
    Date of Patent: May 8, 1990
    Assignee: International Business Machines Corporation
    Inventors: Stamatis Vassiliadis, Michael Putrino, Ann E. Huffman, Brice J. Feal, Gerald G. Pechanek
  • Apparatus for branch prediction for computer instructions
    Patent number: 4914579
    Abstract: An apparatus for branch prediction for computer instructions predicts the outcome of an executing branch instruction in response to instruction operands Q, R, and B. The apparatus includes combinatorial logic for predicting a first branch condition, ((Q+R)-B)>0, or a second branch condition ((Q+R)-B).ltoreq.0.
    Type: Grant
    Filed: February 17, 1988
    Date of Patent: April 3, 1990
    Assignee: International Business Machines Corporation
    Inventors: Michael Putrino, Stamatis Vassiliadis, Ann E. Huffman, Agnes Y. Ngai