Patents by Inventor Ann K. Liao

Ann K. Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of forming buried bit line DRAM circuitry
    Patent number: 7601586
    Abstract: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within the buried bit line forming trench, the bit line vias, and the memory storage node vias within the dielectric mass. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: October 13, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Ann K. Liao, Michael J. Westphal
  • Methods of forming buried bit line DRAM circuitry
    Patent number: 7148102
    Abstract: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within the buried bit line forming trench, the bit line vias, and the memory storage node vias within the dielectric mass. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: December 12, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Ann K. Liao, Michael J. Westphal
  • Methods of forming buried bit line DRAM circuitry
    Patent number: 6939761
    Abstract: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within the buried bit line forming trench, the bit line vias, and the memory storage node vias within the dielectric mass. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: September 6, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Ann K. Liao, Michael J. Westphal
  • Methods of forming buried bit line DRAM circuitry
    Publication number: 20040102027
    Abstract: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within the buried bit line forming trench, the bit line vias, and the memory storage node vias within the dielectric mass. Other aspects and implementations are contemplated.
    Type: Application
    Filed: November 22, 2002
    Publication date: May 27, 2004
    Inventors: Ann K. Liao, Michael J. Westphal