Abstract: A method is provided that can include activating at least two wireless communication channels in parallel, between a first wireless transceiver and a second wireless transceiver. Each of the at least two wireless communication channels can operate at a different radio carrier frequency, and the first wireless transceiver may be part of a first vehicle. The method can also include transmitting, by the first wireless transceiver, common information in parallel on the at least two wireless communication channels to the second wireless transceiver and deactivating the at least two wireless communication channels.

Abstract: There is provided an improved high-voltage generation circuit for use in a mixed signal circuit for multiplying an external power supply potential applied on its input to produce a higher output voltage at an output terminal. The high-voltage generation circuit is formed of a voltage multiplier circuit (114), a voltage comparator circuit (116), and switching circuitry (118). The voltage multiplier circuit is formed of a first stage (122) and at least one second stage (124) connected in series between the input terminal and the output terminal. The second stage is formed of a CMOS transistor (MP4) whose substrate is connected to a controlled node (N23). The voltage comparator circuit compares the external power supply potential and the output voltage and generates a control logic signal.

Abstract: A CMOS power-on reset circuit for generating a reset signal in response to the activation of a power supply includes a voltage clamping stage (14) and a hysteresis switching stage (16). The voltage clamping stage (14) is formed of an N-channel resistor (M1), a first resistor (R1), and a second resistor (R2). The hysteresis switching stage (16) includes a P-channel pull-up transistor (M2), a first N-channel pull-down transistor (M3), a current-source transistor (M4), a second N-channel pull-down transistor (M5), and an inverter (G1).

Abstract: A logic interface circuit for recovering phase and data information from ECL differential input signals of the NRZI type having distorted duty cycles caused by ECL-to-CMOS translators includes first and second ECL-to-CMOS translators (T1, T2), first and second delay circuits, and an output logic circuit The first delay circuit is formed of a first inverter (I1), a first delay network (D1), and a first NAND logic gate (N1). The second delay network includes a second inverter (I2), a second delay network (D2), and a second NAND logic gate (N2). The output logic circuit is formed of a third NAND logic gate. The interface circuit generates an output signal which is in the form of a pulse train whose cycle time can be detected for determining the frequency information and whose presence or absence of pulses can be detected for determining data information.

Abstract: A CMOS digital-controlled delay gate is provided in which the propagation delay time can be precisely controlled by digital select control signals. The delay gate includes an inverter circuit section (12) formed of a plurality of CMOS inverters (12a-12n) each inverter having a P-channel transistor and an N-channel transistor and a control logic section (14, 16) which is responsive to the digital select control signals for changing the ratio of the total P-channel transistor size to the total N-channel transistor size in the enabled transistors. The input threshold voltage of the inverter circuit section is selectively changeable so as to produce a controllable propagation delay.

Abstract: A CMOS gate is provided which has a programmable driving power characteristic so that its propagation delay time can be varied by digital select control signals (S1-Sm). The CMOS gate includes a programmable inverter section (12) formed of a plurality of inverters (12a-12m), a switching logic control section (14), and a static inverter (16). The switching logic control signal section is responsive to the digital select control signals for selectively programming a certain number of the plurality of inverters to be enabled. In this manner, a certain number of the plurality of inverters will be wired in parallel with the static inverter in order to produce the desired amount of propagation delay time.

Abstract: A high-speed CMOS-to-ECL translator circuit for receiving CMOS complementary input signals and for converting the CMOS input signals to ECL differential output signals includes a differential pair of MOS input transistors (N4,N3), a constant current source (I.sub.s), a first output stage, and a second output stage. The first output stage is formed of a first MOS output transistor (N2) and a second MOS output transistor (P1). The second output stage is formed of a third MOS output transistor (N2) and a fourth MOS output transistor (P2). The gates of the first and second input transistors (N4, N3) are responsive to the CMOS complementary input signals (D, DB). The first output stage generates one of the ECL differential output signals (Q) at a first output terminal (18), and the second output stage generates the other one of the ECL differential output signals (QB) at a second output terminal (20).

Abstract: A CMOS tri-mode input buffer for generating three groups of binary codes at first and second output nodes in response to an input signal having three different voltage levels includes an output stage (20), first output buffer (22), a second output buffer (24), a first inptu circuit (26), and a second input circuit (28). The output stage (20) generates first and second output signals (Q1, Q2) at the respective first and second output noes (16, 18). The first output buffer is responsive to the first output signal (Q1) for generating a first buffered input signal (U1) which is CMOS logic compatible. The second output buffer (24) is responsive to the second output signal (Q2) for generating second buffered output signal (U2) which is CMOS logic compatible.

Abstract: A static electricity protection system for use with a voltage sensitive MOS component having a gate input including a layer of oxide. A transmission gate having a source and a drain as an input and output, respectively, is connected to the MOS component gate input for protecting it from sudden electrical voltage surge discharges. The transmission gate source and drain include a layer of oxide substantially thicker than the oxide layer of the MOS component gate input.

Abstract: A static PLA circuit includes a logic gate portion, a precharge circuit portion and a feedback circuit portion. The feedback circuit portion is connected between the output of the logic gate portion and the input of the precharge circuit portion. The feedback circuit portion functions to delay the turn-on time of the precharge circuit portion when the output of the logic gate portion is making a high-to-low transition, thereby increasing the speed of the output transition.