Abstract: A composite material may include a polymer resin layer; and a plurality of rigid plates to reinforce the polymer resin layer, each rigid plate of the plurality of rigid plates having a polygon shape with rigid sides. The plurality of rigid plates may be fabricated in a pattern in the polymer resin layer to form a plurality of hinges in the polymer resin layer between sides of the plurality of rigid plates, so that the composite is foldable at the plurality of hinges into a collapse state and expandable at the plurality of hinges to deploy into a structure.

Abstract: A method of fabricating a plurality of integrated circuits on a substrate according to a first integrated circuit design. Each of the integrated circuits is formed with a plurality of layer patterns. At least one first layer pattern of the layer patterns is common with a second integrated circuit design, and at least one second layer pattern of the layer patterns is unique to the first integrated circuit design. The first layer pattern is imaged on the substrate using an exposure tool and a first mask having a first number of the first layer patterns formed in a block thereon. No other layer patterns of the first layer patterns and the second layer patterns are formed on the first mask. The first number is less than the plurality of integrated circuits formed on the substrate. The first layer patterns are imaged on the substrate by exposing and repeating the block of first number of first layer patterns across the substrate with the exposure tool.

Abstract: A photoresist-free and ARC-free lip on the periphery of the upper surface of a semiconductor substrate adjacent the end edge of the substrate is formed by the steps of: forming an ARC layer on one surface of a semiconductor substrate; chemically treating the ARC layer to chemically terminate the ARC layer a first distance from the end edge of the substrate; forming a photoresist layer over the semiconductor substrate and over the ARC layer thereon; and exposing the peripheral portion of the photoresist layer to UV light followed by development of the exposed peripheral portion of the photoresist layer to photolithographically terminate the photoresist layer a second distance from the end edge of the substrate wherein the second distance is smaller than the first distance.

Abstract: A process for providing a thin encapsulation layer for thin film heads includes controlling the bias voltage of the substrate and head during the encapsulation layer deposition process. The bias voltage is first maintained at approximately 60 volts while the standard encapsulation overcoat portion of the layer is deposited. This may take approximately one hour. Over the next thirty minutes, the bias voltage is ramped from approximately 60 volts to approximately 200 volts in a gradual, linear manner to reduce the stress on the wafer and heads. The bias voltage is then maintained at approximately 200 volts for the next three hours while the remainder of the encapsulation layer is deposited. Because of the higher bias voltage, the layer is deposited in a substantially planar manner so that there is no need for a lapping back process. Stress to the head is minimized by ramping the bias voltage. In addition, relatively short studs can be used for routing signals to and from the read/write elements of the head.