Abstract: The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.

Abstract: The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.

Abstract: An interface connection is described for joining a host device, such as a Network Processor, to peripherals such as modems, printers, local area networks, Ethernets and Token-Ring interfaces. The connection is particularly useful for joining portable computers, such as laptops, to these peripherals. The connector utilizes a programmable Network Processor (NP) either in the host device or in an external fan-out box. This programmable Network Processor adapts the host device to a variety of peripheral devices utilizing different protocols and I/O speeds. The NP can use a Digital Signal Processor to provide programmable services to the physical layers. The host device may contain a high-speed communication interface with the NP contained in the external connection box.

Abstract: A network processor is used for the routing of objects in non-data networking applications. The processor utilizes the Open Shortest Path First (OSPF) algorithm to capitalize on the benefits of data control for object traffic control and costs. A network processor is used at each point in a grid represented by intersecting paths. One or more routing tables are embedded in each network processor. Each routing table describes links with other network processors in the grid to which the network processor is interconnected. A cost factor is associated with each link and is constantly updated by the OSPF as new information becomes available. If a link or route becomes unavailable, the cost is set at infinity. The system then creates an alternative path for the object between a source and the desired destination that bypasses the unavailable link or route.

Abstract: An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell. The standard cell includes a plurality of logic functions. The ASIC also includes at least one bus coupled to at least a portion of the logic functions and a plurality of internal signals from the plurality of logic functions. Finally, the ASIC includes a field programmable (FP) function coupled to the at least one bus and at least a portion of the plurality of internal signals. The FP function provides access to internal signals for observation and control. An ASIC using a field programmable gate array (FPGA) function within a standard cell design is utilized to create an internal-to-the-ASIC bridging of internal signals to observe and control of the internal signals of the ASIC. By the placement of logic, which expresses a test program, into the FPGA function that manipulates the I/O pins and/or other functional entities of interest, the ASIC function and/or surrounding logic can be easily verified.

Abstract: An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises a standard cell, the standard cell including a plurality of logic functions. The ASIC further includes at least one FPGA interconnect coupled to at least a portion of the logic functions. The FPGA interconnect can be configured to select a particular logic function of the plurality of logic functions. An ASIC in accordance with the present invention allows “field selection” of functions that are connected to the internal bus(es) and to external I/O. In addition, functional block connections made with internal buses can be significantly wider and faster than buses brought on chip via external chip I/Os. Further, the ASIC reduces cost because selective bus connections can be made internal to the chip, thus eliminating the need for external pins. Finally, the ASIC reduces the cost of the packaged component by allowing the chip to be packaged in a lower pin count package.

Abstract: A network processor is disclosed. The network processor comprises a plurality of standard cells; and at least one field programmable gate array (FPGA) cell that can communicate with at least one of the standard cells. The at least one FPGA cell can provide a specified function based upon field programming techniques to allow for customization of the network processor. Utilizing a method and system in accordance with the present invention, a network processor can be customized to implement a variety of functions in hardware using embedded FPGA macros. The combined technology of ASIC standard cells plus FPGA cells enables fast time-to-market for new designs while optimizing cost and performance. In addition, the combined ASIC plus FPGA on a single die allows the chip developer to use proven standard cell macros for common logic and programmable cells for high-risk logic.

Abstract: A system, method and program product for optimizing a product order in real time where the product includes at least one customer-selectable component. Component information such as component cost, delivery lag time and availability are determined in real-time by querying a manufacturer system and, in response to a component being unavailable at the manufacturer, querying at least one supplier system that can supply the component to the manufacturer. The customer is then offered at least one order option in real time based on the results of the determination.

Abstract: An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell, the standard cell including a plurality of logic functions. The ASIC also includes an input/output (I/O) configuration function coupled to at least a portion of the logic functions. The ASIC further includes a field programmable gate array (FPGA) function coupled to the I/O configuration function. The FPGA function controls the I/O configuration function based upon a configuration file. A system in accordance with the present invention reduces the cost and time associated with the timing analysis activities during development. An FPGA function within the ASIC is utilized to control the I/O characteristics such as delay, termination and/or slew rate for the I/O pin mapping. Different I/O configurations will be provided by the FPGA function depending on the environment the ASIC is used in.

Abstract: A network processor is used for the routing of objects in non-data networking applications. The processor utilizes the Open Shortest Path First (OSPF) algorithm to capitalize on the benefits of data control for object traffic control and costs. A network processor is used at each point in a grid represented by intersecting paths. One or more routing tables are embedded in each network processor. Each routing table describes links with other network processors in the grid to which the network processor is interconnected. A cost factor is associated with each link and is constantly updated by the OSPF as new information becomes available. If a link or route becomes unavailable, the cost is set at infinity. The system then creates an alternative path for the object between a source and the desired destination that bypasses the unavailable link or route.

Abstract: An interface connection is described for joining a host device, such as a Network Processor, to peripherals such as modems, printers, local area networks, Ethernets and Token-Ring interfaces. The connection is particularly useful for joining portable computers, such as laptops, to these peripherals. The connector utilizes a programmable Network Processor (NP) either in the host device or in an external fan-out box. This programmable Network Processor adapts the host device to a variety of peripheral devices utilizing different protocols and I/O speeds. The NP can use a Digital Signal Processor to provide programmable services to the physical layers. The host device may contain a high-speed communication interface with the NP contained in the external connection box.

Abstract: An integrated circuit comprising a standard cell is disclosed. The standard cell includes a plurality of logic functions; at least a portion of the logic functions requiring initialization. The circuit includes a field programmable gate array (FPGA) cell coupled to the at least a portion of the plurality of logic functions. The at least a portion of the plurality of logic functions are initialized by the FPGA cell. In a method and system in accordance with the present invention, an on-chip Field Programmable Gate Array (FPGA) cell is configured to implement the required application-specific function initializations. The FPGA cell could be wired directly to each of the registers within the functional blocks requiring initialization. These registers would also be wired to the processor bus allowing software access for normal operation after initialization.

Abstract: A network processor is disclosed. The network processor comprises a plurality of standard cells; and at least one field programmable gate array (FPGA) cell that can communicate with at least one of the standard cells. The at least one FPGA cell can provide a specified function based upon field programming techniques to allow for customization of the network processor. Utilizing a method and system in accordance with the present invention, a network processor can be customized to implement a variety of functions in hardware using embedded FPGA macros. The combined technology of ASIC standard cells plus FPGA cells enables fast time-to-market for new designs while optimizing cost and performance. In addition, the combined ASIC plus FPGA on a single die allows the chip developer to use proven standard cell macros for common logic and programmable cells for high-risk logic.

Abstract: An integrated circuit comprising a standard cell is disclosed. The standard cell includes a plurality of logic functions; at least a portion of the logic functions requiring initialization. The circuit includes a field programmable gate array (FPGA) cell coupled to the at least a portion of the plurality of logic functions. The at least a portion of the plurality of logic functions are initialized by the FPGA cell. In a method and system in accordance with the present invention, an on-chip Field Programmable Gate Array (FPGA) cell is configured to implement the required application-specific function initializations. The FPGA cell could be wired directly to each of the registers within the functional blocks requiring initialization. These registers would also be wired to the processor bus allowing software access for normal operation after initialization.

Abstract: A system on a chip (SOC) integrated circuit is disclosed. The SOC integrated circuit includes a plurality of logic functions. The logic functions include a plurality of base functions and a plurality of peripheral functions. The SOC integrated circuit includes at least one field programmable gate array (FPGA) cell that is coupled to the plurality of peripheral functions. The FPGA cell can then be configured to selectively enable the plurality of peripheral functions. Accordingly, one or more FPGA cells are provided on an SOC. The FPGA cells can then be selectively configured to enable one or more peripheral chip functions. Because FPGAs are customized “in the field”, i.e., in a specific customer application, one SOC part number containing all peripheral functions can be used to satisfy multiple customer markets.

Abstract: An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell. The standard cell includes a plurality of logic functions. The ASIC also includes at least one bus coupled to at least a portion of the logic functions and a plurality of internal signals from the plurality of logic functions. Finally, the ASIC includes a field programmable (FP) function coupled to the at least one bus and at least a portion of the plurality of internal signals. The FP function provides access to internal signals for observation and control. An ASIC using a field programmable gate array (FPGA) function within a standard cell design is utilized to create an internal-to-the-ASIC bridging of internal signals to observe and control of the internal signals of the ASIC. By the placement of logic, which expresses a test program, into the FPGA function that manipulates the I/O pins and/or other functional entities of interest, the ASIC function and/or surrounding logic can be easily verified.

Abstract: An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell. The standard cell includes a plurality of logic functions and at least one bus coupled to at least a portion of the logic functions. The standard cell also includes a plurality of internal signals from the plurality of logic functions and a field programmable gate array (FPGA) function coupled to the at least one bus and at least a portion of the plurality of internal signals. The FPGA function includes a debug client function that observes and manipulates the at least one bus and the plurality of internal signals. A system and method in accordance with the present invention utilizes a debug function within a standard cell design to create an internal-to-the-ASIC debugging (software, hardware or both) function. The system and method is provided by connection of internal buses and signals of interest to a debug client function within the FPGA function.

Abstract: An application specific integrated circuit (ASIC) is disclosed. The ASIC includes a standard cell, the standard cell including a plurality of logic functions. The ASIC also includes an input/output (I/O) configuration function coupled to at least a portion of the logic functions. The ASIC further includes a field programmable gate array (FPGA) function coupled to the I/O configuration function. The FPGA function controls the I/O configuration function based upon a configuration file. A system in accordance with the present invention reduces the cost and time associated with the timing analysis activities during development. An FPGA function within the ASIC is utilized to control the I/O characteristics such as delay, termination and/or slew rate for the I/O pin mapping. Different I/O configurations will be provided by the FPGA function depending on the environment the ASIC is used in.

Abstract: An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises a standard cell, the standard cell including a plurality of logic functions. The ASIC further includes at least one FPGA interconnect coupled to at least a portion of the logic functions. The FPGA interconnect can be configured to select a particular logic function of the plurality of logic functions. An ASIC in accordance with the present invention allows “field selection” of functions that are connected to the internal bus(es) and to external I/O. In addition, functional block connections made with internal buses can be significantly wider and faster than buses brought on chip via external chip I/Os. Further, the ASIC reduces cost because selective bus connections can be made internal to the chip, thus eliminating the need for external pins. Finally, the ASIC reduces the cost of the packaged component by allowing the chip to be packaged in a lower pin count package.

Abstract: A method, system and computer program product for using a variable pricing structure for transmitting packets across a communications link. A variable pricing structure including a plurality of pricing options may be generated by a processor in a gateway by counting the number of packets received from a customer as well as analyzing those received packets. The generated variable pricing structure embodied in a billing record may be transmitted to the customer. The customer upon receiving the billing record may select a pricing option based on one or more criteria, e.g., file size, transmission rate. The packets to be transmitted by the customer to a network device via the gateway may be temporarily stored by an equipment coupled to the customer if the one or more criteria upon which the selected pricing option is based exceed a threshold value thereby ensuring that the customer does not incur extra charges.