Patents by Inventor Ann Sekli Chin

Ann Sekli Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7587444
    Abstract: A data processing apparatus for summing data values includes: a plurality of adder logic stages arranged in parallel; a control logic, in response to a request to sum two data values, to forward portions of the two data values to respective ones of the plurality of adder logic stages, each of the plurality of adder logic stages performing a carry propagate addition of the received portions to generate an intermediate sum, a propagate value and a carry; and further logic stages for combining the intermediate sums, carries and propagate values to produce a sum of the two data values. The control logic, further in response to a request to add a third data value to the sum before the further logic has completed sum, forwards portions of the third data value to respective ones of the plurality of adder logic stages, feedbacks the intermediate sums, and selectively feedbacks a carry generated from a preceding adder logic stage.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: September 8, 2009
    Assignee: ARM Limited
    Inventors: Micah Rone McDaniel, Ann Sekli Chin, Daniel Kershaw
  • Patent number: 7437544
    Abstract: A data processing apparatus and method are provided for executing a sequence of instructions including at least one multiple iteration instruction. The data processing apparatus comprises an instruction store for storing the sequence of instructions, and a processing unit for executing the sequence of instructions, the processing unit comprising at least a first processing path and a second processing path to enable at least two instructions of the sequence to be executed in parallel. When executing instructions in parallel, the first processing path executes an instruction which is earlier in the sequence than the instruction executing in the second processing path. The processing unit is operable when executing a multiple iteration instruction to allow a first iteration of the multiple iteration instruction to be executed in either the first processing path or the second processing path, but to cause all remaining iterations of the multiple iteration instruction to be executed in the first processing path.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: October 14, 2008
    Assignee: ARM Limited
    Inventors: Ann Sekli Chin, David James Williamson